diff mbox series

Revert "Optimize v4sf reduction.".

Message ID 20210927074841.2188391-1-hongtao.liu@intel.com
State New
Headers show
Series Revert "Optimize v4sf reduction.". | expand

Commit Message

liuhongt Sept. 27, 2021, 7:48 a.m. UTC 
Revert due to performace regression.

This reverts commit 8f323c712ea76cc4506b03895e9b991e4e4b2baf.

     PR target/102473
     PR target/101059
---
 gcc/config/i386/sse.md                        | 39 ++++++-------------
 gcc/testsuite/gcc.target/i386/sse2-pr101059.c | 32 ---------------
 gcc/testsuite/gcc.target/i386/sse3-pr101059.c | 13 -------
 3 files changed, 11 insertions(+), 73 deletions(-)
 delete mode 100644 gcc/testsuite/gcc.target/i386/sse2-pr101059.c
 delete mode 100644 gcc/testsuite/gcc.target/i386/sse3-pr101059.c
diff mbox series

Patch

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index a446dedb2ec..bb7600edbab 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -3156,36 +3156,19 @@  (define_insn "sse3_h<insn>v4sf3"
    (set_attr "prefix_rep" "1,*")
    (set_attr "mode" "V4SF")])
 
-(define_expand "reduc_plus_scal_v4sf"
- [(plus:V4SF
-   (match_operand:SF 0 "register_operand")
-   (match_operand:V4SF 1 "register_operand"))]
- "TARGET_SSE"
-{
-  rtx vtmp = gen_reg_rtx (V4SFmode);
-  rtx stmp = gen_reg_rtx (SFmode);
-  if (TARGET_SSE3)
-    emit_insn (gen_sse3_movshdup (vtmp, operands[1]));
-  else
-    emit_insn (gen_sse_shufps (vtmp, operands[1], operands[1], GEN_INT(177)));
+(define_mode_iterator REDUC_SSE_PLUS_MODE
+ [(V2DF "TARGET_SSE") (V4SF "TARGET_SSE")])
 
-  emit_insn (gen_addv4sf3 (operands[1], operands[1], vtmp));
-  emit_insn (gen_sse_movhlps (vtmp, vtmp, operands[1]));
-  emit_insn (gen_vec_extractv4sfsf (stmp, vtmp, const0_rtx));
-  emit_insn (gen_vec_extractv4sfsf (operands[0], operands[1], const0_rtx));
-  emit_insn (gen_addsf3 (operands[0], operands[0], stmp));
-  DONE;
-})
-
-(define_expand "reduc_plus_scal_v2df"
- [(plus:V2DF
-   (match_operand:DF 0 "register_operand")
-   (match_operand:V2DF 1 "register_operand"))]
- "TARGET_SSE"
+(define_expand "reduc_plus_scal_<mode>"
+ [(plus:REDUC_SSE_PLUS_MODE
+   (match_operand:<ssescalarmode> 0 "register_operand")
+   (match_operand:REDUC_SSE_PLUS_MODE 1 "register_operand"))]
+ ""
 {
-  rtx tmp = gen_reg_rtx (V2DFmode);
-  ix86_expand_reduc (gen_addv2df3, tmp, operands[1]);
-  emit_insn (gen_vec_extractv2dfdf (operands[0], tmp, const0_rtx));
+  rtx tmp = gen_reg_rtx (<MODE>mode);
+  ix86_expand_reduc (gen_add<mode>3, tmp, operands[1]);
+  emit_insn (gen_vec_extract<mode><ssescalarmodelower> (operands[0], tmp,
+                                                        const0_rtx));
   DONE;
 })
 
diff --git a/gcc/testsuite/gcc.target/i386/sse2-pr101059.c b/gcc/testsuite/gcc.target/i386/sse2-pr101059.c
deleted file mode 100644
index d155bf5b43c..00000000000
--- a/gcc/testsuite/gcc.target/i386/sse2-pr101059.c
+++ /dev/null
@@ -1,32 +0,0 @@ 
-/* { dg-do run } */
-/* { dg-options "-O2 -ffast-math -msse2" } */
-/* { dg-require-effective-target sse2 } */
-
-#ifndef CHECK_H
-#define CHECK_H "sse2-check.h"
-#endif
-
-#ifndef TEST
-#define TEST sse2_test
-#endif
-
-#include CHECK_H
-
-float
-__attribute__((noipa, optimize("tree-vectorize")))
-foo (float* p)
-{
-  float sum = 0.f;
-  for (int i = 0; i != 4; i++)
-    sum += p[i];
-  return sum;
-}
-
-static void
-TEST (void)
-{
-  float p[4] = {1.0f, 2.0f, 3.0f, 4.0f};
-  float res = foo (p);
-  if (res != 10.0f)
-    abort();
-}
diff --git a/gcc/testsuite/gcc.target/i386/sse3-pr101059.c b/gcc/testsuite/gcc.target/i386/sse3-pr101059.c
deleted file mode 100644
index 4795e892883..00000000000
--- a/gcc/testsuite/gcc.target/i386/sse3-pr101059.c
+++ /dev/null
@@ -1,13 +0,0 @@ 
-/* { dg-do run } */
-/* { dg-options "-O2 -ffast-math -msse3" } */
-/* { dg-require-effective-target sse3 } */
-
-#ifndef CHECK_H
-#define CHECK_H "sse3-check.h"
-#endif
-
-#ifndef TEST
-#define TEST sse3_test
-#endif
-
-#include "sse2-pr101059.c"