From patchwork Tue Aug 24 10:59:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Earnshaw X-Patchwork-Id: 1520232 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=AI3a+ra7; dkim-atps=neutral Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Gv5lx0qxSz9sXk for ; Tue, 24 Aug 2021 21:02:05 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9098C3858421 for ; Tue, 24 Aug 2021 11:02:01 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9098C3858421 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1629802921; bh=avS7veV0uuiwAEMxUmC4X9O9AUHN5Em5wVoGYfGCHOc=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=AI3a+ra7I3mTmptNs54xDzN900seYF8t7ZmXK7m3/VpOkBivLa/GVQq3J+MNDF/uP VsjAnwi6hMUSy8id5Zd5gOTFKZwJUOHFyDzaDztq9n1OhpAWfhqYPHS0pxldwDxGKP dvlG524TDZxPN8a6lZXWgG08wbHI+4dmDg3iFzZw= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id D97FB3858416 for ; Tue, 24 Aug 2021 10:59:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D97FB3858416 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7AEF014BF; Tue, 24 Aug 2021 03:59:50 -0700 (PDT) Received: from e126323.arm.com (unknown [10.57.39.244]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 00A9F3F66F; Tue, 24 Aug 2021 03:59:49 -0700 (PDT) To: gcc-patches@gcc.gnu.org Subject: [committed 4/6] arm: add erratum mitigation to __gnu_cmse_nonsecure_call [PR102035] Date: Tue, 24 Aug 2021 11:59:26 +0100 Message-Id: <20210824105928.3869183-5-rearnsha@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210824105928.3869183-1-rearnsha@arm.com> References: <20210824105928.3869183-1-rearnsha@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Earnshaw via Gcc-patches From: Richard Earnshaw Reply-To: Richard Earnshaw Cc: Richard Earnshaw Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Add the recommended erratum mitigation sequence to __gnu_cmse_nonsecure_call for use on Armv8-m.main devices. Since this is in the library code we cannot know in advance whether the core we are running on will be affected by this, so always enable it. libgcc: PR target/102035 * config/arm/cmse_nonsecure_call.S (__gnu_cmse_nonsecure_call): Add vlldm erratum work-around. --- libgcc/config/arm/cmse_nonsecure_call.S | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/libgcc/config/arm/cmse_nonsecure_call.S b/libgcc/config/arm/cmse_nonsecure_call.S index 00830ade98e..c8e0fbbe665 100644 --- a/libgcc/config/arm/cmse_nonsecure_call.S +++ b/libgcc/config/arm/cmse_nonsecure_call.S @@ -102,6 +102,11 @@ blxns r4 #ifdef __ARM_PCS_VFP vpop.f64 {d8-d15} #else +/* VLLDM erratum mitigation sequence. */ +mrs r5, control +tst r5, #8 /* CONTROL_S.SFPA */ +it ne +.inst.w 0xeeb00a40 /* vmovne s0, s0 */ vlldm sp /* Lazy restore of d0-d16 and FPSCR. */ add sp, sp, #0x88 /* Free space used to save floating point registers. */ #endif /* __ARM_PCS_VFP */