diff mbox series

[46/62] AVX512FP16: Enable FP16 mask load/store.

Message ID 20210701061648.9447-47-hongtao.liu@intel.com
State New
Headers show
Series Support all AVX512FP16 intrinsics. | expand

Commit Message

Liu, Hongtao July 1, 2021, 6:16 a.m. UTC 
From: "H.J. Lu" <hjl.tools@gmail.com>

gcc/ChangeLog:

	* config/i386/sse.md (avx512fmaskmodelower): Extend to support
	HF modes.
	(maskload<mode><avx512fmaskmodelower>): Ditto.
	(maskstore<mode><avx512fmaskmodelower>): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx512fp16-xorsign-1.c: New test.
---
 gcc/config/i386/sse.md                        | 13 +++---
 .../gcc.target/i386/avx512fp16-xorsign-1.c    | 41 +++++++++++++++++++
 2 files changed, 48 insertions(+), 6 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-xorsign-1.c
diff mbox series

Patch

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 7c594babcce..cbf1e75c0b2 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -915,6 +915,7 @@  (define_mode_attr avx512fmaskmodelower
    (V32HI "si") (V16HI "hi") (V8HI  "qi") (V4HI "qi")
    (V16SI "hi") (V8SI  "qi") (V4SI  "qi")
    (V8DI  "qi") (V4DI  "qi") (V2DI  "qi")
+   (V32HF "si") (V16HF "hi") (V8HF  "qi")
    (V16SF "hi") (V8SF  "qi") (V4SF  "qi")
    (V8DF  "qi") (V4DF  "qi") (V2DF  "qi")])
 
@@ -23106,9 +23107,9 @@  (define_expand "maskload<mode><sseintvecmodelower>"
   "TARGET_AVX")
 
 (define_expand "maskload<mode><avx512fmaskmodelower>"
-  [(set (match_operand:V48_AVX512VL 0 "register_operand")
-	(vec_merge:V48_AVX512VL
-	  (match_operand:V48_AVX512VL 1 "memory_operand")
+  [(set (match_operand:V48H_AVX512VL 0 "register_operand")
+	(vec_merge:V48H_AVX512VL
+	  (match_operand:V48H_AVX512VL 1 "memory_operand")
 	  (match_dup 0)
 	  (match_operand:<avx512fmaskmode> 2 "register_operand")))]
   "TARGET_AVX512F")
@@ -23131,9 +23132,9 @@  (define_expand "maskstore<mode><sseintvecmodelower>"
   "TARGET_AVX")
 
 (define_expand "maskstore<mode><avx512fmaskmodelower>"
-  [(set (match_operand:V48_AVX512VL 0 "memory_operand")
-	(vec_merge:V48_AVX512VL
-	  (match_operand:V48_AVX512VL 1 "register_operand")
+  [(set (match_operand:V48H_AVX512VL 0 "memory_operand")
+	(vec_merge:V48H_AVX512VL
+	  (match_operand:V48H_AVX512VL 1 "register_operand")
 	  (match_dup 0)
 	  (match_operand:<avx512fmaskmode> 2 "register_operand")))]
   "TARGET_AVX512F")
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-xorsign-1.c b/gcc/testsuite/gcc.target/i386/avx512fp16-xorsign-1.c
new file mode 100644
index 00000000000..a22a6ceabff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-xorsign-1.c
@@ -0,0 +1,41 @@ 
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512vl -ftree-vectorize -fdump-tree-vect-details -save-temps" } */
+
+extern void abort ();
+
+static void do_test (void);
+
+#define DO_TEST do_test
+#define AVX512FP16
+#include "avx512-check.h"
+
+#define N 16
+_Float16 a[N] = {-0.1f, -3.2f, -6.3f, -9.4f,
+		 -12.5f, -15.6f, -18.7f, -21.8f,
+		 24.9f, 27.1f, 30.2f, 33.3f,
+		 36.4f, 39.5f, 42.6f, 45.7f};
+_Float16 b[N] = {-1.2f, 3.4f, -5.6f, 7.8f,
+		 -9.0f, 1.0f, -2.0f, 3.0f,
+		 -4.0f, -5.0f, 6.0f, 7.0f,
+		 -8.0f, -9.0f, 10.0f, 11.0f};
+_Float16 r[N];
+
+static void
+__attribute__ ((noinline, noclone))
+do_test (void)
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+    r[i] = a[i] * __builtin_copysignf16 (1.0f, b[i]);
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    if (r[i] != a[i] * __builtin_copysignf16 (1.0f, b[i]))
+      abort ();
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { scan-assembler "\[ \t\]xor" } } */
+/* { dg-final { scan-assembler "\[ \t\]and" } } */
+/* { dg-final { scan-assembler-not "copysign" } } */