| Message ID | 20210701061648.9447-45-hongtao.liu@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | Support all AVX512FP16 intrinsics. | expand |
On Thu, Jul 1, 2021 at 2:18 PM liuhongt <hongtao.liu@intel.com> wrote: > > From: "H.J. Lu" <hjl.tools@gmail.com> > > 1. FP16 vector xor/ior/and/andnot/abs/neg > 2. FP16 scalar abs/neg/copysign/xorsign > > gcc/ChangeLog: > > * config/i386/i386-expand.c (ix86_expand_fp_absneg_operator): > Handle HFmode. > (ix86_expand_copysign): Ditto. > (ix86_expand_xorsign): Ditto. > * config/i386/i386.c (ix86_build_const_vector): Handle HF vector > modes. > (ix86_build_signbit_mask): Ditto. > (ix86_can_change_mode_class): Ditto. > * config/i386/i386.md (SSEMODEF): Add HF mode. > (ssevecmodef): Ditto. > (<code><mode>2): Use MODEFH. > (*<code><mode>2_1): Ditto. > (define_split): Ditto. > (xorsign<mode>3): Ditto. > (@xorsign<mode>3_1): Ditto. As mentioned by uros, l think these also better have separate patterns for hf. > * config/i386/sse.md (VFB): New mode iterator. > (VFB_128_256): Ditto. > (VFB_512): Ditto. > (sseintvecmode2): Support HF vector mode. > (<code><mode>2): Use new mode iterator. > (*<code><mode>2): Ditto. > (copysign<mode>3): Ditto. > (xorsign<mode>3): Ditto. > (<code><mode>3<mask_name>): Ditto. > (<code><mode>3<mask_name>): Ditto. > (<sse>_andnot<mode>3<mask_name>): Adjust for HF vector mode. > (<sse>_andnot<mode>3<mask_name>): Ditto. > (*<code><mode>3<mask_name>): Ditto. > (*<code><mode>3<mask_name>): Ditto. > --- > gcc/config/i386/i386-expand.c | 12 +++- > gcc/config/i386/i386.c | 12 +++- > gcc/config/i386/i386.md | 40 ++++++----- > gcc/config/i386/sse.md | 128 ++++++++++++++++++++-------------- > 4 files changed, 118 insertions(+), 74 deletions(-) > > diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c > index 9233c6cd1e8..006f4bec8db 100644 > --- a/gcc/config/i386/i386-expand.c > +++ b/gcc/config/i386/i386-expand.c > @@ -1781,6 +1781,8 @@ ix86_expand_fp_absneg_operator (enum rtx_code code, machine_mode mode, > vmode = V4SFmode; > else if (mode == DFmode) > vmode = V2DFmode; > + else if (mode == HFmode) > + vmode = V8HFmode; > } > > dst = operands[0]; > @@ -1918,7 +1920,9 @@ ix86_expand_copysign (rtx operands[]) > > mode = GET_MODE (dest); > > - if (mode == SFmode) > + if (mode == HFmode) > + vmode = V8HFmode; > + else if (mode == SFmode) > vmode = V4SFmode; > else if (mode == DFmode) > vmode = V2DFmode; > @@ -1934,7 +1938,7 @@ ix86_expand_copysign (rtx operands[]) > if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0))) > op0 = simplify_unary_operation (ABS, mode, op0, mode); > > - if (mode == SFmode || mode == DFmode) > + if (mode == HFmode || mode == SFmode || mode == DFmode) > { > if (op0 == CONST0_RTX (mode)) > op0 = CONST0_RTX (vmode); > @@ -2073,7 +2077,9 @@ ix86_expand_xorsign (rtx operands[]) > > mode = GET_MODE (dest); > > - if (mode == SFmode) > + if (mode == HFmode) > + vmode = V8HFmode; > + else if (mode == SFmode) > vmode = V4SFmode; > else if (mode == DFmode) > vmode = V2DFmode; > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c > index dc0d440061b..17e1b5ea874 100644 > --- a/gcc/config/i386/i386.c > +++ b/gcc/config/i386/i386.c > @@ -15374,6 +15374,9 @@ ix86_build_const_vector (machine_mode mode, bool vect, rtx value) > case E_V2DImode: > gcc_assert (vect); > /* FALLTHRU */ > + case E_V8HFmode: > + case E_V16HFmode: > + case E_V32HFmode: > case E_V16SFmode: > case E_V8SFmode: > case E_V4SFmode: > @@ -15412,6 +15415,13 @@ ix86_build_signbit_mask (machine_mode mode, bool vect, bool invert) > > switch (mode) > { > + case E_V8HFmode: > + case E_V16HFmode: > + case E_V32HFmode: > + vec_mode = mode; > + imode = HImode; > + break; > + > case E_V16SImode: > case E_V16SFmode: > case E_V8SImode: > @@ -19198,7 +19208,7 @@ ix86_can_change_mode_class (machine_mode from, machine_mode to, > disallow a change to these modes, reload will assume it's ok to > drop the subreg from (subreg:SI (reg:HI 100) 0). This affects > the vec_dupv4hi pattern. */ > - if (GET_MODE_SIZE (from) < 4) > + if (GET_MODE_SIZE (from) < 4 && from != E_HFmode) > return false; > } > > diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md > index 014aba187e1..a85c23d74f1 100644 > --- a/gcc/config/i386/i386.md > +++ b/gcc/config/i386/i386.md > @@ -1233,9 +1233,10 @@ (define_mode_iterator MODEFH [(HF "TARGET_AVX512FP16") SF DF]) > ;; All x87 floating point modes plus HFmode > (define_mode_iterator X87MODEFH [HF SF DF XF]) > > -;; All SSE floating point modes > -(define_mode_iterator SSEMODEF [SF DF TF]) > -(define_mode_attr ssevecmodef [(SF "V4SF") (DF "V2DF") (TF "TF")]) > +;; All SSE floating point modes and HFmode > +(define_mode_iterator SSEMODEF [HF SF DF TF]) > +(define_mode_attr ssevecmodef [(HF "V8HF") (SF "V4SF") (DF "V2DF") (TF "TF")]) > + > > ;; SSE instruction suffix for various modes > (define_mode_attr ssemodesuffix > @@ -10529,8 +10530,8 @@ (define_insn_and_split "*nabstf2_1" > [(set_attr "isa" "noavx,noavx,avx,avx")]) > > (define_expand "<code><mode>2" > - [(set (match_operand:X87MODEF 0 "register_operand") > - (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand")))] > + [(set (match_operand:X87MODEFH 0 "register_operand") > + (absneg:X87MODEFH (match_operand:X87MODEFH 1 "register_operand")))] > "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)" > "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;") > > @@ -10559,9 +10560,9 @@ (define_split > "ix86_split_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;") > > (define_insn "*<code><mode>2_1" > - [(set (match_operand:MODEF 0 "register_operand" "=x,x,Yv,f,!r") > - (absneg:MODEF > - (match_operand:MODEF 1 "register_operand" "0,x,Yv,0,0"))) > + [(set (match_operand:MODEFH 0 "register_operand" "=x,x,Yv,f,!r") > + (absneg:MODEFH > + (match_operand:MODEFH 1 "register_operand" "0,x,Yv,0,0"))) > (use (match_operand:<ssevecmode> 2 "vector_operand" "xBm,0,Yvm,X,X")) > (clobber (reg:CC FLAGS_REG))] > "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)" > @@ -10572,7 +10573,8 @@ (define_insn "*<code><mode>2_1" > (match_test ("SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH")) > (if_then_else > (eq_attr "alternative" "3,4") > - (symbol_ref "TARGET_MIX_SSE_I387") > + (symbol_ref "TARGET_MIX_SSE_I387 > + && <MODE>mode != HFmode") > (const_string "*")) > (if_then_else > (eq_attr "alternative" "3,4") > @@ -10580,9 +10582,9 @@ (define_insn "*<code><mode>2_1" > (symbol_ref "false"))))]) > > (define_split > - [(set (match_operand:MODEF 0 "sse_reg_operand") > - (absneg:MODEF > - (match_operand:MODEF 1 "sse_reg_operand"))) > + [(set (match_operand:MODEFH 0 "sse_reg_operand") > + (absneg:MODEFH > + (match_operand:MODEFH 1 "sse_reg_operand"))) > (use (match_operand:<ssevecmodef> 2 "vector_operand")) > (clobber (reg:CC FLAGS_REG))] > "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH > @@ -10706,17 +10708,17 @@ (define_split > "ix86_split_copysign_var (operands); DONE;") > > (define_expand "xorsign<mode>3" > - [(match_operand:MODEF 0 "register_operand") > - (match_operand:MODEF 1 "register_operand") > - (match_operand:MODEF 2 "register_operand")] > + [(match_operand:MODEFH 0 "register_operand") > + (match_operand:MODEFH 1 "register_operand") > + (match_operand:MODEFH 2 "register_operand")] > "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH" > "ix86_expand_xorsign (operands); DONE;") > > (define_insn_and_split "@xorsign<mode>3_1" > - [(set (match_operand:MODEF 0 "register_operand" "=Yv") > - (unspec:MODEF > - [(match_operand:MODEF 1 "register_operand" "Yv") > - (match_operand:MODEF 2 "register_operand" "0") > + [(set (match_operand:MODEFH 0 "register_operand" "=Yv") > + (unspec:MODEFH > + [(match_operand:MODEFH 1 "register_operand" "Yv") > + (match_operand:MODEFH 2 "register_operand" "0") > (match_operand:<ssevecmode> 3 "nonimmediate_operand" "Yvm")] > UNSPEC_XORSIGN))] > "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH" > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index fdcc0515228..7c594babcce 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -317,11 +317,26 @@ (define_mode_iterator VFH > (V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF > (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) > > +;; 128-, 256- and 512-bit float vector modes for bitwise operations > +(define_mode_iterator VFB > + [(V32HF "TARGET_AVX512FP16") > + (V16HF "TARGET_AVX512FP16") > + (V8HF "TARGET_AVX512FP16") > + (V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF > + (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) > + > ;; 128- and 256-bit float vector modes > (define_mode_iterator VF_128_256 > [(V8SF "TARGET_AVX") V4SF > (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) > > +;; 128- and 256-bit float vector modes for bitwise operations > +(define_mode_iterator VFB_128_256 > + [(V16HF "TARGET_AVX512FP16") > + (V8HF "TARGET_AVX512FP16") > + (V8SF "TARGET_AVX") V4SF > + (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) > + > ;; All SFmode vector float modes > (define_mode_iterator VF1 > [(V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF]) > @@ -374,6 +389,10 @@ (define_mode_iterator VF_256 > (define_mode_iterator VF_512 > [V16SF V8DF]) > > +;; All 512bit vector float modes for bitwise operations > +(define_mode_iterator VFB_512 > + [(V32HF "TARGET_AVX512FP16") V16SF V8DF]) > + > (define_mode_iterator VI48_AVX512VL > [V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") > V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) > @@ -923,7 +942,8 @@ (define_mode_attr sseintvecmode > > (define_mode_attr sseintvecmode2 > [(V8DF "XI") (V4DF "OI") (V2DF "TI") > - (V8SF "OI") (V4SF "TI")]) > + (V8SF "OI") (V4SF "TI") > + (V16HF "OI") (V8HF "TI")]) > > (define_mode_attr sseintvecmodelower > [(V16SF "v16si") (V8DF "v8di") > @@ -1968,22 +1988,22 @@ (define_insn "kunpckdi" > ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; > > (define_expand "<code><mode>2" > - [(set (match_operand:VF 0 "register_operand") > - (absneg:VF > - (match_operand:VF 1 "register_operand")))] > + [(set (match_operand:VFB 0 "register_operand") > + (absneg:VFB > + (match_operand:VFB 1 "register_operand")))] > "TARGET_SSE" > "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;") > > (define_insn_and_split "*<code><mode>2" > - [(set (match_operand:VF 0 "register_operand" "=x,x,v,v") > - (absneg:VF > - (match_operand:VF 1 "vector_operand" "0,xBm,v,m"))) > - (use (match_operand:VF 2 "vector_operand" "xBm,0,vm,v"))] > + [(set (match_operand:VFB 0 "register_operand" "=x,x,v,v") > + (absneg:VFB > + (match_operand:VFB 1 "vector_operand" "0,xBm,v,m"))) > + (use (match_operand:VFB 2 "vector_operand" "xBm,0,vm,v"))] > "TARGET_SSE" > "#" > "&& reload_completed" > [(set (match_dup 0) > - (<absneg_op>:VF (match_dup 1) (match_dup 2)))] > + (<absneg_op>:VFB (match_dup 1) (match_dup 2)))] > { > if (TARGET_AVX) > { > @@ -3893,11 +3913,11 @@ (define_expand "vcond_mask_<mode><sseintvecmodelower>" > ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; > > (define_insn "<sse>_andnot<mode>3<mask_name>" > - [(set (match_operand:VF_128_256 0 "register_operand" "=x,x,v,v") > - (and:VF_128_256 > - (not:VF_128_256 > - (match_operand:VF_128_256 1 "register_operand" "0,x,v,v")) > - (match_operand:VF_128_256 2 "vector_operand" "xBm,xm,vm,vm")))] > + [(set (match_operand:VFB_128_256 0 "register_operand" "=x,x,v,v") > + (and:VFB_128_256 > + (not:VFB_128_256 > + (match_operand:VFB_128_256 1 "register_operand" "0,x,v,v")) > + (match_operand:VFB_128_256 2 "vector_operand" "xBm,xm,vm,vm")))] > "TARGET_SSE && <mask_avx512vl_condition>" > { > char buf[128]; > @@ -3920,6 +3940,8 @@ (define_insn "<sse>_andnot<mode>3<mask_name>" > > switch (get_attr_mode (insn)) > { > + case MODE_V16HF: > + case MODE_V8HF: > case MODE_V8SF: > case MODE_V4SF: > suffix = "ps"; > @@ -3958,11 +3980,11 @@ (define_insn "<sse>_andnot<mode>3<mask_name>" > (const_string "<MODE>")))]) > > (define_insn "<sse>_andnot<mode>3<mask_name>" > - [(set (match_operand:VF_512 0 "register_operand" "=v") > - (and:VF_512 > - (not:VF_512 > - (match_operand:VF_512 1 "register_operand" "v")) > - (match_operand:VF_512 2 "nonimmediate_operand" "vm")))] > + [(set (match_operand:VFB_512 0 "register_operand" "=v") > + (and:VFB_512 > + (not:VFB_512 > + (match_operand:VFB_512 1 "register_operand" "v")) > + (match_operand:VFB_512 2 "nonimmediate_operand" "vm")))] > "TARGET_AVX512F" > { > char buf[128]; > @@ -3972,8 +3994,9 @@ (define_insn "<sse>_andnot<mode>3<mask_name>" > suffix = "<ssemodesuffix>"; > ops = ""; > > - /* There is no vandnp[sd] in avx512f. Use vpandn[qd]. */ > - if (!TARGET_AVX512DQ) > + /* Since there are no vandnp[sd] without AVX512DQ nor vandnph, > + use vp<logic>[dq]. */ > + if (!TARGET_AVX512DQ || <MODE>mode == V32HFmode) > { > suffix = GET_MODE_INNER (<MODE>mode) == DFmode ? "q" : "d"; > ops = "p"; > @@ -3993,26 +4016,26 @@ (define_insn "<sse>_andnot<mode>3<mask_name>" > (const_string "XI")))]) > > (define_expand "<code><mode>3<mask_name>" > - [(set (match_operand:VF_128_256 0 "register_operand") > - (any_logic:VF_128_256 > - (match_operand:VF_128_256 1 "vector_operand") > - (match_operand:VF_128_256 2 "vector_operand")))] > + [(set (match_operand:VFB_128_256 0 "register_operand") > + (any_logic:VFB_128_256 > + (match_operand:VFB_128_256 1 "vector_operand") > + (match_operand:VFB_128_256 2 "vector_operand")))] > "TARGET_SSE && <mask_avx512vl_condition>" > "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") > > (define_expand "<code><mode>3<mask_name>" > - [(set (match_operand:VF_512 0 "register_operand") > - (any_logic:VF_512 > - (match_operand:VF_512 1 "nonimmediate_operand") > - (match_operand:VF_512 2 "nonimmediate_operand")))] > + [(set (match_operand:VFB_512 0 "register_operand") > + (any_logic:VFB_512 > + (match_operand:VFB_512 1 "nonimmediate_operand") > + (match_operand:VFB_512 2 "nonimmediate_operand")))] > "TARGET_AVX512F" > "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") > > (define_insn "*<code><mode>3<mask_name>" > - [(set (match_operand:VF_128_256 0 "register_operand" "=x,x,v,v") > - (any_logic:VF_128_256 > - (match_operand:VF_128_256 1 "vector_operand" "%0,x,v,v") > - (match_operand:VF_128_256 2 "vector_operand" "xBm,xm,vm,vm")))] > + [(set (match_operand:VFB_128_256 0 "register_operand" "=x,x,v,v") > + (any_logic:VFB_128_256 > + (match_operand:VFB_128_256 1 "vector_operand" "%0,x,v,v") > + (match_operand:VFB_128_256 2 "vector_operand" "xBm,xm,vm,vm")))] > "TARGET_SSE && <mask_avx512vl_condition> > && !(MEM_P (operands[1]) && MEM_P (operands[2]))" > { > @@ -4036,6 +4059,8 @@ (define_insn "*<code><mode>3<mask_name>" > > switch (get_attr_mode (insn)) > { > + case MODE_V16HF: > + case MODE_V8HF: > case MODE_V8SF: > case MODE_V4SF: > suffix = "ps"; > @@ -4074,10 +4099,10 @@ (define_insn "*<code><mode>3<mask_name>" > (const_string "<MODE>")))]) > > (define_insn "*<code><mode>3<mask_name>" > - [(set (match_operand:VF_512 0 "register_operand" "=v") > - (any_logic:VF_512 > - (match_operand:VF_512 1 "nonimmediate_operand" "%v") > - (match_operand:VF_512 2 "nonimmediate_operand" "vm")))] > + [(set (match_operand:VFB_512 0 "register_operand" "=v") > + (any_logic:VFB_512 > + (match_operand:VFB_512 1 "nonimmediate_operand" "%v") > + (match_operand:VFB_512 2 "nonimmediate_operand" "vm")))] > "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))" > { > char buf[128]; > @@ -4087,8 +4112,9 @@ (define_insn "*<code><mode>3<mask_name>" > suffix = "<ssemodesuffix>"; > ops = ""; > > - /* There is no v<logic>p[sd] in avx512f. Use vp<logic>[dq]. */ > - if (!TARGET_AVX512DQ) > + /* Since there are no v<logic>p[sd] without AVX512DQ nor v<logic>ph, > + use vp<logic>[dq]. */ > + if (!TARGET_AVX512DQ || <MODE>mode == V32HFmode) > { > suffix = GET_MODE_INNER (<MODE>mode) == DFmode ? "q" : "d"; > ops = "p"; > @@ -4109,14 +4135,14 @@ (define_insn "*<code><mode>3<mask_name>" > > (define_expand "copysign<mode>3" > [(set (match_dup 4) > - (and:VF > - (not:VF (match_dup 3)) > - (match_operand:VF 1 "vector_operand"))) > + (and:VFB > + (not:VFB (match_dup 3)) > + (match_operand:VFB 1 "vector_operand"))) > (set (match_dup 5) > - (and:VF (match_dup 3) > - (match_operand:VF 2 "vector_operand"))) > - (set (match_operand:VF 0 "register_operand") > - (ior:VF (match_dup 4) (match_dup 5)))] > + (and:VFB (match_dup 3) > + (match_operand:VFB 2 "vector_operand"))) > + (set (match_operand:VFB 0 "register_operand") > + (ior:VFB (match_dup 4) (match_dup 5)))] > "TARGET_SSE" > { > operands[3] = ix86_build_signbit_mask (<MODE>mode, 1, 0); > @@ -4127,11 +4153,11 @@ (define_expand "copysign<mode>3" > > (define_expand "xorsign<mode>3" > [(set (match_dup 4) > - (and:VF (match_dup 3) > - (match_operand:VF 2 "vector_operand"))) > - (set (match_operand:VF 0 "register_operand") > - (xor:VF (match_dup 4) > - (match_operand:VF 1 "vector_operand")))] > + (and:VFB (match_dup 3) > + (match_operand:VFB 2 "vector_operand"))) > + (set (match_operand:VFB 0 "register_operand") > + (xor:VFB (match_dup 4) > + (match_operand:VFB 1 "vector_operand")))] > "TARGET_SSE" > { > operands[3] = ix86_build_signbit_mask (<MODE>mode, 1, 0); > -- > 2.18.1 >
On Fri, Jul 23, 2021 at 1:13 PM Hongtao Liu <crazylht@gmail.com> wrote: > > On Thu, Jul 1, 2021 at 2:18 PM liuhongt <hongtao.liu@intel.com> wrote: > > > > From: "H.J. Lu" <hjl.tools@gmail.com> > > > > 1. FP16 vector xor/ior/and/andnot/abs/neg > > 2. FP16 scalar abs/neg/copysign/xorsign > > > > gcc/ChangeLog: > > > > * config/i386/i386-expand.c (ix86_expand_fp_absneg_operator): > > Handle HFmode. > > (ix86_expand_copysign): Ditto. > > (ix86_expand_xorsign): Ditto. > > * config/i386/i386.c (ix86_build_const_vector): Handle HF vector > > modes. > > (ix86_build_signbit_mask): Ditto. > > (ix86_can_change_mode_class): Ditto. > > * config/i386/i386.md (SSEMODEF): Add HF mode. > > (ssevecmodef): Ditto. > > (<code><mode>2): Use MODEFH. > > (*<code><mode>2_1): Ditto. > > (define_split): Ditto. > > (xorsign<mode>3): Ditto. > > (@xorsign<mode>3_1): Ditto. > As mentioned by uros, l think these also better have separate patterns for hf. I realized there're parameters names in define_insn and define_insn_and_split, and they will be called by xorsign/copysign functions in i386-expand.c, for simplicity i'd like to keep the macroization of HF patterns in this patch. > > * config/i386/sse.md (VFB): New mode iterator. > > (VFB_128_256): Ditto. > > (VFB_512): Ditto. > > (sseintvecmode2): Support HF vector mode. > > (<code><mode>2): Use new mode iterator. > > (*<code><mode>2): Ditto. > > (copysign<mode>3): Ditto. > > (xorsign<mode>3): Ditto. > > (<code><mode>3<mask_name>): Ditto. > > (<code><mode>3<mask_name>): Ditto. > > (<sse>_andnot<mode>3<mask_name>): Adjust for HF vector mode. > > (<sse>_andnot<mode>3<mask_name>): Ditto. > > (*<code><mode>3<mask_name>): Ditto. > > (*<code><mode>3<mask_name>): Ditto. > > --- > > gcc/config/i386/i386-expand.c | 12 +++- > > gcc/config/i386/i386.c | 12 +++- > > gcc/config/i386/i386.md | 40 ++++++----- > > gcc/config/i386/sse.md | 128 ++++++++++++++++++++-------------- > > 4 files changed, 118 insertions(+), 74 deletions(-) > > > > diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c > > index 9233c6cd1e8..006f4bec8db 100644 > > --- a/gcc/config/i386/i386-expand.c > > +++ b/gcc/config/i386/i386-expand.c > > @@ -1781,6 +1781,8 @@ ix86_expand_fp_absneg_operator (enum rtx_code code, machine_mode mode, > > vmode = V4SFmode; > > else if (mode == DFmode) > > vmode = V2DFmode; > > + else if (mode == HFmode) > > + vmode = V8HFmode; > > } > > > > dst = operands[0]; > > @@ -1918,7 +1920,9 @@ ix86_expand_copysign (rtx operands[]) > > > > mode = GET_MODE (dest); > > > > - if (mode == SFmode) > > + if (mode == HFmode) > > + vmode = V8HFmode; > > + else if (mode == SFmode) > > vmode = V4SFmode; > > else if (mode == DFmode) > > vmode = V2DFmode; > > @@ -1934,7 +1938,7 @@ ix86_expand_copysign (rtx operands[]) > > if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0))) > > op0 = simplify_unary_operation (ABS, mode, op0, mode); > > > > - if (mode == SFmode || mode == DFmode) > > + if (mode == HFmode || mode == SFmode || mode == DFmode) > > { > > if (op0 == CONST0_RTX (mode)) > > op0 = CONST0_RTX (vmode); > > @@ -2073,7 +2077,9 @@ ix86_expand_xorsign (rtx operands[]) > > > > mode = GET_MODE (dest); > > > > - if (mode == SFmode) > > + if (mode == HFmode) > > + vmode = V8HFmode; > > + else if (mode == SFmode) > > vmode = V4SFmode; > > else if (mode == DFmode) > > vmode = V2DFmode; > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c > > index dc0d440061b..17e1b5ea874 100644 > > --- a/gcc/config/i386/i386.c > > +++ b/gcc/config/i386/i386.c > > @@ -15374,6 +15374,9 @@ ix86_build_const_vector (machine_mode mode, bool vect, rtx value) > > case E_V2DImode: > > gcc_assert (vect); > > /* FALLTHRU */ > > + case E_V8HFmode: > > + case E_V16HFmode: > > + case E_V32HFmode: > > case E_V16SFmode: > > case E_V8SFmode: > > case E_V4SFmode: > > @@ -15412,6 +15415,13 @@ ix86_build_signbit_mask (machine_mode mode, bool vect, bool invert) > > > > switch (mode) > > { > > + case E_V8HFmode: > > + case E_V16HFmode: > > + case E_V32HFmode: > > + vec_mode = mode; > > + imode = HImode; > > + break; > > + > > case E_V16SImode: > > case E_V16SFmode: > > case E_V8SImode: > > @@ -19198,7 +19208,7 @@ ix86_can_change_mode_class (machine_mode from, machine_mode to, > > disallow a change to these modes, reload will assume it's ok to > > drop the subreg from (subreg:SI (reg:HI 100) 0). This affects > > the vec_dupv4hi pattern. */ > > - if (GET_MODE_SIZE (from) < 4) > > + if (GET_MODE_SIZE (from) < 4 && from != E_HFmode) > > return false; > > } > > > > diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md > > index 014aba187e1..a85c23d74f1 100644 > > --- a/gcc/config/i386/i386.md > > +++ b/gcc/config/i386/i386.md > > @@ -1233,9 +1233,10 @@ (define_mode_iterator MODEFH [(HF "TARGET_AVX512FP16") SF DF]) > > ;; All x87 floating point modes plus HFmode > > (define_mode_iterator X87MODEFH [HF SF DF XF]) > > > > -;; All SSE floating point modes > > -(define_mode_iterator SSEMODEF [SF DF TF]) > > -(define_mode_attr ssevecmodef [(SF "V4SF") (DF "V2DF") (TF "TF")]) > > +;; All SSE floating point modes and HFmode > > +(define_mode_iterator SSEMODEF [HF SF DF TF]) > > +(define_mode_attr ssevecmodef [(HF "V8HF") (SF "V4SF") (DF "V2DF") (TF "TF")]) > > + > > > > ;; SSE instruction suffix for various modes > > (define_mode_attr ssemodesuffix > > @@ -10529,8 +10530,8 @@ (define_insn_and_split "*nabstf2_1" > > [(set_attr "isa" "noavx,noavx,avx,avx")]) > > > > (define_expand "<code><mode>2" > > - [(set (match_operand:X87MODEF 0 "register_operand") > > - (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand")))] > > + [(set (match_operand:X87MODEFH 0 "register_operand") > > + (absneg:X87MODEFH (match_operand:X87MODEFH 1 "register_operand")))] > > "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)" > > "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;") > > > > @@ -10559,9 +10560,9 @@ (define_split > > "ix86_split_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;") > > > > (define_insn "*<code><mode>2_1" > > - [(set (match_operand:MODEF 0 "register_operand" "=x,x,Yv,f,!r") > > - (absneg:MODEF > > - (match_operand:MODEF 1 "register_operand" "0,x,Yv,0,0"))) > > + [(set (match_operand:MODEFH 0 "register_operand" "=x,x,Yv,f,!r") > > + (absneg:MODEFH > > + (match_operand:MODEFH 1 "register_operand" "0,x,Yv,0,0"))) > > (use (match_operand:<ssevecmode> 2 "vector_operand" "xBm,0,Yvm,X,X")) > > (clobber (reg:CC FLAGS_REG))] > > "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)" > > @@ -10572,7 +10573,8 @@ (define_insn "*<code><mode>2_1" > > (match_test ("SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH")) > > (if_then_else > > (eq_attr "alternative" "3,4") > > - (symbol_ref "TARGET_MIX_SSE_I387") > > + (symbol_ref "TARGET_MIX_SSE_I387 > > + && <MODE>mode != HFmode") > > (const_string "*")) > > (if_then_else > > (eq_attr "alternative" "3,4") > > @@ -10580,9 +10582,9 @@ (define_insn "*<code><mode>2_1" > > (symbol_ref "false"))))]) > > > > (define_split > > - [(set (match_operand:MODEF 0 "sse_reg_operand") > > - (absneg:MODEF > > - (match_operand:MODEF 1 "sse_reg_operand"))) > > + [(set (match_operand:MODEFH 0 "sse_reg_operand") > > + (absneg:MODEFH > > + (match_operand:MODEFH 1 "sse_reg_operand"))) > > (use (match_operand:<ssevecmodef> 2 "vector_operand")) > > (clobber (reg:CC FLAGS_REG))] > > "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH > > @@ -10706,17 +10708,17 @@ (define_split > > "ix86_split_copysign_var (operands); DONE;") > > > > (define_expand "xorsign<mode>3" > > - [(match_operand:MODEF 0 "register_operand") > > - (match_operand:MODEF 1 "register_operand") > > - (match_operand:MODEF 2 "register_operand")] > > + [(match_operand:MODEFH 0 "register_operand") > > + (match_operand:MODEFH 1 "register_operand") > > + (match_operand:MODEFH 2 "register_operand")] > > "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH" > > "ix86_expand_xorsign (operands); DONE;") > > > > (define_insn_and_split "@xorsign<mode>3_1" > > - [(set (match_operand:MODEF 0 "register_operand" "=Yv") > > - (unspec:MODEF > > - [(match_operand:MODEF 1 "register_operand" "Yv") > > - (match_operand:MODEF 2 "register_operand" "0") > > + [(set (match_operand:MODEFH 0 "register_operand" "=Yv") > > + (unspec:MODEFH > > + [(match_operand:MODEFH 1 "register_operand" "Yv") > > + (match_operand:MODEFH 2 "register_operand" "0") > > (match_operand:<ssevecmode> 3 "nonimmediate_operand" "Yvm")] > > UNSPEC_XORSIGN))] > > "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH" > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > > index fdcc0515228..7c594babcce 100644 > > --- a/gcc/config/i386/sse.md > > +++ b/gcc/config/i386/sse.md > > @@ -317,11 +317,26 @@ (define_mode_iterator VFH > > (V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF > > (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) > > > > +;; 128-, 256- and 512-bit float vector modes for bitwise operations > > +(define_mode_iterator VFB > > + [(V32HF "TARGET_AVX512FP16") > > + (V16HF "TARGET_AVX512FP16") > > + (V8HF "TARGET_AVX512FP16") > > + (V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF > > + (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) > > + > > ;; 128- and 256-bit float vector modes > > (define_mode_iterator VF_128_256 > > [(V8SF "TARGET_AVX") V4SF > > (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) > > > > +;; 128- and 256-bit float vector modes for bitwise operations > > +(define_mode_iterator VFB_128_256 > > + [(V16HF "TARGET_AVX512FP16") > > + (V8HF "TARGET_AVX512FP16") > > + (V8SF "TARGET_AVX") V4SF > > + (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) > > + > > ;; All SFmode vector float modes > > (define_mode_iterator VF1 > > [(V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF]) > > @@ -374,6 +389,10 @@ (define_mode_iterator VF_256 > > (define_mode_iterator VF_512 > > [V16SF V8DF]) > > > > +;; All 512bit vector float modes for bitwise operations > > +(define_mode_iterator VFB_512 > > + [(V32HF "TARGET_AVX512FP16") V16SF V8DF]) > > + > > (define_mode_iterator VI48_AVX512VL > > [V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") > > V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) > > @@ -923,7 +942,8 @@ (define_mode_attr sseintvecmode > > > > (define_mode_attr sseintvecmode2 > > [(V8DF "XI") (V4DF "OI") (V2DF "TI") > > - (V8SF "OI") (V4SF "TI")]) > > + (V8SF "OI") (V4SF "TI") > > + (V16HF "OI") (V8HF "TI")]) > > > > (define_mode_attr sseintvecmodelower > > [(V16SF "v16si") (V8DF "v8di") > > @@ -1968,22 +1988,22 @@ (define_insn "kunpckdi" > > ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; > > > > (define_expand "<code><mode>2" > > - [(set (match_operand:VF 0 "register_operand") > > - (absneg:VF > > - (match_operand:VF 1 "register_operand")))] > > + [(set (match_operand:VFB 0 "register_operand") > > + (absneg:VFB > > + (match_operand:VFB 1 "register_operand")))] > > "TARGET_SSE" > > "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;") > > > > (define_insn_and_split "*<code><mode>2" > > - [(set (match_operand:VF 0 "register_operand" "=x,x,v,v") > > - (absneg:VF > > - (match_operand:VF 1 "vector_operand" "0,xBm,v,m"))) > > - (use (match_operand:VF 2 "vector_operand" "xBm,0,vm,v"))] > > + [(set (match_operand:VFB 0 "register_operand" "=x,x,v,v") > > + (absneg:VFB > > + (match_operand:VFB 1 "vector_operand" "0,xBm,v,m"))) > > + (use (match_operand:VFB 2 "vector_operand" "xBm,0,vm,v"))] > > "TARGET_SSE" > > "#" > > "&& reload_completed" > > [(set (match_dup 0) > > - (<absneg_op>:VF (match_dup 1) (match_dup 2)))] > > + (<absneg_op>:VFB (match_dup 1) (match_dup 2)))] > > { > > if (TARGET_AVX) > > { > > @@ -3893,11 +3913,11 @@ (define_expand "vcond_mask_<mode><sseintvecmodelower>" > > ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; > > > > (define_insn "<sse>_andnot<mode>3<mask_name>" > > - [(set (match_operand:VF_128_256 0 "register_operand" "=x,x,v,v") > > - (and:VF_128_256 > > - (not:VF_128_256 > > - (match_operand:VF_128_256 1 "register_operand" "0,x,v,v")) > > - (match_operand:VF_128_256 2 "vector_operand" "xBm,xm,vm,vm")))] > > + [(set (match_operand:VFB_128_256 0 "register_operand" "=x,x,v,v") > > + (and:VFB_128_256 > > + (not:VFB_128_256 > > + (match_operand:VFB_128_256 1 "register_operand" "0,x,v,v")) > > + (match_operand:VFB_128_256 2 "vector_operand" "xBm,xm,vm,vm")))] > > "TARGET_SSE && <mask_avx512vl_condition>" > > { > > char buf[128]; > > @@ -3920,6 +3940,8 @@ (define_insn "<sse>_andnot<mode>3<mask_name>" > > > > switch (get_attr_mode (insn)) > > { > > + case MODE_V16HF: > > + case MODE_V8HF: > > case MODE_V8SF: > > case MODE_V4SF: > > suffix = "ps"; > > @@ -3958,11 +3980,11 @@ (define_insn "<sse>_andnot<mode>3<mask_name>" > > (const_string "<MODE>")))]) > > > > (define_insn "<sse>_andnot<mode>3<mask_name>" > > - [(set (match_operand:VF_512 0 "register_operand" "=v") > > - (and:VF_512 > > - (not:VF_512 > > - (match_operand:VF_512 1 "register_operand" "v")) > > - (match_operand:VF_512 2 "nonimmediate_operand" "vm")))] > > + [(set (match_operand:VFB_512 0 "register_operand" "=v") > > + (and:VFB_512 > > + (not:VFB_512 > > + (match_operand:VFB_512 1 "register_operand" "v")) > > + (match_operand:VFB_512 2 "nonimmediate_operand" "vm")))] > > "TARGET_AVX512F" > > { > > char buf[128]; > > @@ -3972,8 +3994,9 @@ (define_insn "<sse>_andnot<mode>3<mask_name>" > > suffix = "<ssemodesuffix>"; > > ops = ""; > > > > - /* There is no vandnp[sd] in avx512f. Use vpandn[qd]. */ > > - if (!TARGET_AVX512DQ) > > + /* Since there are no vandnp[sd] without AVX512DQ nor vandnph, > > + use vp<logic>[dq]. */ > > + if (!TARGET_AVX512DQ || <MODE>mode == V32HFmode) > > { > > suffix = GET_MODE_INNER (<MODE>mode) == DFmode ? "q" : "d"; > > ops = "p"; > > @@ -3993,26 +4016,26 @@ (define_insn "<sse>_andnot<mode>3<mask_name>" > > (const_string "XI")))]) > > > > (define_expand "<code><mode>3<mask_name>" > > - [(set (match_operand:VF_128_256 0 "register_operand") > > - (any_logic:VF_128_256 > > - (match_operand:VF_128_256 1 "vector_operand") > > - (match_operand:VF_128_256 2 "vector_operand")))] > > + [(set (match_operand:VFB_128_256 0 "register_operand") > > + (any_logic:VFB_128_256 > > + (match_operand:VFB_128_256 1 "vector_operand") > > + (match_operand:VFB_128_256 2 "vector_operand")))] > > "TARGET_SSE && <mask_avx512vl_condition>" > > "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") > > > > (define_expand "<code><mode>3<mask_name>" > > - [(set (match_operand:VF_512 0 "register_operand") > > - (any_logic:VF_512 > > - (match_operand:VF_512 1 "nonimmediate_operand") > > - (match_operand:VF_512 2 "nonimmediate_operand")))] > > + [(set (match_operand:VFB_512 0 "register_operand") > > + (any_logic:VFB_512 > > + (match_operand:VFB_512 1 "nonimmediate_operand") > > + (match_operand:VFB_512 2 "nonimmediate_operand")))] > > "TARGET_AVX512F" > > "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") > > > > (define_insn "*<code><mode>3<mask_name>" > > - [(set (match_operand:VF_128_256 0 "register_operand" "=x,x,v,v") > > - (any_logic:VF_128_256 > > - (match_operand:VF_128_256 1 "vector_operand" "%0,x,v,v") > > - (match_operand:VF_128_256 2 "vector_operand" "xBm,xm,vm,vm")))] > > + [(set (match_operand:VFB_128_256 0 "register_operand" "=x,x,v,v") > > + (any_logic:VFB_128_256 > > + (match_operand:VFB_128_256 1 "vector_operand" "%0,x,v,v") > > + (match_operand:VFB_128_256 2 "vector_operand" "xBm,xm,vm,vm")))] > > "TARGET_SSE && <mask_avx512vl_condition> > > && !(MEM_P (operands[1]) && MEM_P (operands[2]))" > > { > > @@ -4036,6 +4059,8 @@ (define_insn "*<code><mode>3<mask_name>" > > > > switch (get_attr_mode (insn)) > > { > > + case MODE_V16HF: > > + case MODE_V8HF: > > case MODE_V8SF: > > case MODE_V4SF: > > suffix = "ps"; > > @@ -4074,10 +4099,10 @@ (define_insn "*<code><mode>3<mask_name>" > > (const_string "<MODE>")))]) > > > > (define_insn "*<code><mode>3<mask_name>" > > - [(set (match_operand:VF_512 0 "register_operand" "=v") > > - (any_logic:VF_512 > > - (match_operand:VF_512 1 "nonimmediate_operand" "%v") > > - (match_operand:VF_512 2 "nonimmediate_operand" "vm")))] > > + [(set (match_operand:VFB_512 0 "register_operand" "=v") > > + (any_logic:VFB_512 > > + (match_operand:VFB_512 1 "nonimmediate_operand" "%v") > > + (match_operand:VFB_512 2 "nonimmediate_operand" "vm")))] > > "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))" > > { > > char buf[128]; > > @@ -4087,8 +4112,9 @@ (define_insn "*<code><mode>3<mask_name>" > > suffix = "<ssemodesuffix>"; > > ops = ""; > > > > - /* There is no v<logic>p[sd] in avx512f. Use vp<logic>[dq]. */ > > - if (!TARGET_AVX512DQ) > > + /* Since there are no v<logic>p[sd] without AVX512DQ nor v<logic>ph, > > + use vp<logic>[dq]. */ > > + if (!TARGET_AVX512DQ || <MODE>mode == V32HFmode) > > { > > suffix = GET_MODE_INNER (<MODE>mode) == DFmode ? "q" : "d"; > > ops = "p"; > > @@ -4109,14 +4135,14 @@ (define_insn "*<code><mode>3<mask_name>" > > > > (define_expand "copysign<mode>3" > > [(set (match_dup 4) > > - (and:VF > > - (not:VF (match_dup 3)) > > - (match_operand:VF 1 "vector_operand"))) > > + (and:VFB > > + (not:VFB (match_dup 3)) > > + (match_operand:VFB 1 "vector_operand"))) > > (set (match_dup 5) > > - (and:VF (match_dup 3) > > - (match_operand:VF 2 "vector_operand"))) > > - (set (match_operand:VF 0 "register_operand") > > - (ior:VF (match_dup 4) (match_dup 5)))] > > + (and:VFB (match_dup 3) > > + (match_operand:VFB 2 "vector_operand"))) > > + (set (match_operand:VFB 0 "register_operand") > > + (ior:VFB (match_dup 4) (match_dup 5)))] > > "TARGET_SSE" > > { > > operands[3] = ix86_build_signbit_mask (<MODE>mode, 1, 0); > > @@ -4127,11 +4153,11 @@ (define_expand "copysign<mode>3" > > > > (define_expand "xorsign<mode>3" > > [(set (match_dup 4) > > - (and:VF (match_dup 3) > > - (match_operand:VF 2 "vector_operand"))) > > - (set (match_operand:VF 0 "register_operand") > > - (xor:VF (match_dup 4) > > - (match_operand:VF 1 "vector_operand")))] > > + (and:VFB (match_dup 3) > > + (match_operand:VFB 2 "vector_operand"))) > > + (set (match_operand:VFB 0 "register_operand") > > + (xor:VFB (match_dup 4) > > + (match_operand:VFB 1 "vector_operand")))] > > "TARGET_SSE" > > { > > operands[3] = ix86_build_signbit_mask (<MODE>mode, 1, 0); > > -- > > 2.18.1 > > > > > -- > BR, > Hongtao -- BR, Hongtao
diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index 9233c6cd1e8..006f4bec8db 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -1781,6 +1781,8 @@ ix86_expand_fp_absneg_operator (enum rtx_code code, machine_mode mode, vmode = V4SFmode; else if (mode == DFmode) vmode = V2DFmode; + else if (mode == HFmode) + vmode = V8HFmode; } dst = operands[0]; @@ -1918,7 +1920,9 @@ ix86_expand_copysign (rtx operands[]) mode = GET_MODE (dest); - if (mode == SFmode) + if (mode == HFmode) + vmode = V8HFmode; + else if (mode == SFmode) vmode = V4SFmode; else if (mode == DFmode) vmode = V2DFmode; @@ -1934,7 +1938,7 @@ ix86_expand_copysign (rtx operands[]) if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0))) op0 = simplify_unary_operation (ABS, mode, op0, mode); - if (mode == SFmode || mode == DFmode) + if (mode == HFmode || mode == SFmode || mode == DFmode) { if (op0 == CONST0_RTX (mode)) op0 = CONST0_RTX (vmode); @@ -2073,7 +2077,9 @@ ix86_expand_xorsign (rtx operands[]) mode = GET_MODE (dest); - if (mode == SFmode) + if (mode == HFmode) + vmode = V8HFmode; + else if (mode == SFmode) vmode = V4SFmode; else if (mode == DFmode) vmode = V2DFmode; diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index dc0d440061b..17e1b5ea874 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -15374,6 +15374,9 @@ ix86_build_const_vector (machine_mode mode, bool vect, rtx value) case E_V2DImode: gcc_assert (vect); /* FALLTHRU */ + case E_V8HFmode: + case E_V16HFmode: + case E_V32HFmode: case E_V16SFmode: case E_V8SFmode: case E_V4SFmode: @@ -15412,6 +15415,13 @@ ix86_build_signbit_mask (machine_mode mode, bool vect, bool invert) switch (mode) { + case E_V8HFmode: + case E_V16HFmode: + case E_V32HFmode: + vec_mode = mode; + imode = HImode; + break; + case E_V16SImode: case E_V16SFmode: case E_V8SImode: @@ -19198,7 +19208,7 @@ ix86_can_change_mode_class (machine_mode from, machine_mode to, disallow a change to these modes, reload will assume it's ok to drop the subreg from (subreg:SI (reg:HI 100) 0). This affects the vec_dupv4hi pattern. */ - if (GET_MODE_SIZE (from) < 4) + if (GET_MODE_SIZE (from) < 4 && from != E_HFmode) return false; } diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 014aba187e1..a85c23d74f1 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1233,9 +1233,10 @@ (define_mode_iterator MODEFH [(HF "TARGET_AVX512FP16") SF DF]) ;; All x87 floating point modes plus HFmode (define_mode_iterator X87MODEFH [HF SF DF XF]) -;; All SSE floating point modes -(define_mode_iterator SSEMODEF [SF DF TF]) -(define_mode_attr ssevecmodef [(SF "V4SF") (DF "V2DF") (TF "TF")]) +;; All SSE floating point modes and HFmode +(define_mode_iterator SSEMODEF [HF SF DF TF]) +(define_mode_attr ssevecmodef [(HF "V8HF") (SF "V4SF") (DF "V2DF") (TF "TF")]) + ;; SSE instruction suffix for various modes (define_mode_attr ssemodesuffix @@ -10529,8 +10530,8 @@ (define_insn_and_split "*nabstf2_1" [(set_attr "isa" "noavx,noavx,avx,avx")]) (define_expand "<code><mode>2" - [(set (match_operand:X87MODEF 0 "register_operand") - (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand")))] + [(set (match_operand:X87MODEFH 0 "register_operand") + (absneg:X87MODEFH (match_operand:X87MODEFH 1 "register_operand")))] "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)" "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;") @@ -10559,9 +10560,9 @@ (define_split "ix86_split_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;") (define_insn "*<code><mode>2_1" - [(set (match_operand:MODEF 0 "register_operand" "=x,x,Yv,f,!r") - (absneg:MODEF - (match_operand:MODEF 1 "register_operand" "0,x,Yv,0,0"))) + [(set (match_operand:MODEFH 0 "register_operand" "=x,x,Yv,f,!r") + (absneg:MODEFH + (match_operand:MODEFH 1 "register_operand" "0,x,Yv,0,0"))) (use (match_operand:<ssevecmode> 2 "vector_operand" "xBm,0,Yvm,X,X")) (clobber (reg:CC FLAGS_REG))] "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)" @@ -10572,7 +10573,8 @@ (define_insn "*<code><mode>2_1" (match_test ("SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH")) (if_then_else (eq_attr "alternative" "3,4") - (symbol_ref "TARGET_MIX_SSE_I387") + (symbol_ref "TARGET_MIX_SSE_I387 + && <MODE>mode != HFmode") (const_string "*")) (if_then_else (eq_attr "alternative" "3,4") @@ -10580,9 +10582,9 @@ (define_insn "*<code><mode>2_1" (symbol_ref "false"))))]) (define_split - [(set (match_operand:MODEF 0 "sse_reg_operand") - (absneg:MODEF - (match_operand:MODEF 1 "sse_reg_operand"))) + [(set (match_operand:MODEFH 0 "sse_reg_operand") + (absneg:MODEFH + (match_operand:MODEFH 1 "sse_reg_operand"))) (use (match_operand:<ssevecmodef> 2 "vector_operand")) (clobber (reg:CC FLAGS_REG))] "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH @@ -10706,17 +10708,17 @@ (define_split "ix86_split_copysign_var (operands); DONE;") (define_expand "xorsign<mode>3" - [(match_operand:MODEF 0 "register_operand") - (match_operand:MODEF 1 "register_operand") - (match_operand:MODEF 2 "register_operand")] + [(match_operand:MODEFH 0 "register_operand") + (match_operand:MODEFH 1 "register_operand") + (match_operand:MODEFH 2 "register_operand")] "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH" "ix86_expand_xorsign (operands); DONE;") (define_insn_and_split "@xorsign<mode>3_1" - [(set (match_operand:MODEF 0 "register_operand" "=Yv") - (unspec:MODEF - [(match_operand:MODEF 1 "register_operand" "Yv") - (match_operand:MODEF 2 "register_operand" "0") + [(set (match_operand:MODEFH 0 "register_operand" "=Yv") + (unspec:MODEFH + [(match_operand:MODEFH 1 "register_operand" "Yv") + (match_operand:MODEFH 2 "register_operand" "0") (match_operand:<ssevecmode> 3 "nonimmediate_operand" "Yvm")] UNSPEC_XORSIGN))] "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH" diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index fdcc0515228..7c594babcce 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -317,11 +317,26 @@ (define_mode_iterator VFH (V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) +;; 128-, 256- and 512-bit float vector modes for bitwise operations +(define_mode_iterator VFB + [(V32HF "TARGET_AVX512FP16") + (V16HF "TARGET_AVX512FP16") + (V8HF "TARGET_AVX512FP16") + (V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF + (V8DF "TARGET_AVX512F") (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) + ;; 128- and 256-bit float vector modes (define_mode_iterator VF_128_256 [(V8SF "TARGET_AVX") V4SF (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) +;; 128- and 256-bit float vector modes for bitwise operations +(define_mode_iterator VFB_128_256 + [(V16HF "TARGET_AVX512FP16") + (V8HF "TARGET_AVX512FP16") + (V8SF "TARGET_AVX") V4SF + (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")]) + ;; All SFmode vector float modes (define_mode_iterator VF1 [(V16SF "TARGET_AVX512F") (V8SF "TARGET_AVX") V4SF]) @@ -374,6 +389,10 @@ (define_mode_iterator VF_256 (define_mode_iterator VF_512 [V16SF V8DF]) +;; All 512bit vector float modes for bitwise operations +(define_mode_iterator VFB_512 + [(V32HF "TARGET_AVX512FP16") V16SF V8DF]) + (define_mode_iterator VI48_AVX512VL [V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) @@ -923,7 +942,8 @@ (define_mode_attr sseintvecmode (define_mode_attr sseintvecmode2 [(V8DF "XI") (V4DF "OI") (V2DF "TI") - (V8SF "OI") (V4SF "TI")]) + (V8SF "OI") (V4SF "TI") + (V16HF "OI") (V8HF "TI")]) (define_mode_attr sseintvecmodelower [(V16SF "v16si") (V8DF "v8di") @@ -1968,22 +1988,22 @@ (define_insn "kunpckdi" ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (define_expand "<code><mode>2" - [(set (match_operand:VF 0 "register_operand") - (absneg:VF - (match_operand:VF 1 "register_operand")))] + [(set (match_operand:VFB 0 "register_operand") + (absneg:VFB + (match_operand:VFB 1 "register_operand")))] "TARGET_SSE" "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;") (define_insn_and_split "*<code><mode>2" - [(set (match_operand:VF 0 "register_operand" "=x,x,v,v") - (absneg:VF - (match_operand:VF 1 "vector_operand" "0,xBm,v,m"))) - (use (match_operand:VF 2 "vector_operand" "xBm,0,vm,v"))] + [(set (match_operand:VFB 0 "register_operand" "=x,x,v,v") + (absneg:VFB + (match_operand:VFB 1 "vector_operand" "0,xBm,v,m"))) + (use (match_operand:VFB 2 "vector_operand" "xBm,0,vm,v"))] "TARGET_SSE" "#" "&& reload_completed" [(set (match_dup 0) - (<absneg_op>:VF (match_dup 1) (match_dup 2)))] + (<absneg_op>:VFB (match_dup 1) (match_dup 2)))] { if (TARGET_AVX) { @@ -3893,11 +3913,11 @@ (define_expand "vcond_mask_<mode><sseintvecmodelower>" ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (define_insn "<sse>_andnot<mode>3<mask_name>" - [(set (match_operand:VF_128_256 0 "register_operand" "=x,x,v,v") - (and:VF_128_256 - (not:VF_128_256 - (match_operand:VF_128_256 1 "register_operand" "0,x,v,v")) - (match_operand:VF_128_256 2 "vector_operand" "xBm,xm,vm,vm")))] + [(set (match_operand:VFB_128_256 0 "register_operand" "=x,x,v,v") + (and:VFB_128_256 + (not:VFB_128_256 + (match_operand:VFB_128_256 1 "register_operand" "0,x,v,v")) + (match_operand:VFB_128_256 2 "vector_operand" "xBm,xm,vm,vm")))] "TARGET_SSE && <mask_avx512vl_condition>" { char buf[128]; @@ -3920,6 +3940,8 @@ (define_insn "<sse>_andnot<mode>3<mask_name>" switch (get_attr_mode (insn)) { + case MODE_V16HF: + case MODE_V8HF: case MODE_V8SF: case MODE_V4SF: suffix = "ps"; @@ -3958,11 +3980,11 @@ (define_insn "<sse>_andnot<mode>3<mask_name>" (const_string "<MODE>")))]) (define_insn "<sse>_andnot<mode>3<mask_name>" - [(set (match_operand:VF_512 0 "register_operand" "=v") - (and:VF_512 - (not:VF_512 - (match_operand:VF_512 1 "register_operand" "v")) - (match_operand:VF_512 2 "nonimmediate_operand" "vm")))] + [(set (match_operand:VFB_512 0 "register_operand" "=v") + (and:VFB_512 + (not:VFB_512 + (match_operand:VFB_512 1 "register_operand" "v")) + (match_operand:VFB_512 2 "nonimmediate_operand" "vm")))] "TARGET_AVX512F" { char buf[128]; @@ -3972,8 +3994,9 @@ (define_insn "<sse>_andnot<mode>3<mask_name>" suffix = "<ssemodesuffix>"; ops = ""; - /* There is no vandnp[sd] in avx512f. Use vpandn[qd]. */ - if (!TARGET_AVX512DQ) + /* Since there are no vandnp[sd] without AVX512DQ nor vandnph, + use vp<logic>[dq]. */ + if (!TARGET_AVX512DQ || <MODE>mode == V32HFmode) { suffix = GET_MODE_INNER (<MODE>mode) == DFmode ? "q" : "d"; ops = "p"; @@ -3993,26 +4016,26 @@ (define_insn "<sse>_andnot<mode>3<mask_name>" (const_string "XI")))]) (define_expand "<code><mode>3<mask_name>" - [(set (match_operand:VF_128_256 0 "register_operand") - (any_logic:VF_128_256 - (match_operand:VF_128_256 1 "vector_operand") - (match_operand:VF_128_256 2 "vector_operand")))] + [(set (match_operand:VFB_128_256 0 "register_operand") + (any_logic:VFB_128_256 + (match_operand:VFB_128_256 1 "vector_operand") + (match_operand:VFB_128_256 2 "vector_operand")))] "TARGET_SSE && <mask_avx512vl_condition>" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") (define_expand "<code><mode>3<mask_name>" - [(set (match_operand:VF_512 0 "register_operand") - (any_logic:VF_512 - (match_operand:VF_512 1 "nonimmediate_operand") - (match_operand:VF_512 2 "nonimmediate_operand")))] + [(set (match_operand:VFB_512 0 "register_operand") + (any_logic:VFB_512 + (match_operand:VFB_512 1 "nonimmediate_operand") + (match_operand:VFB_512 2 "nonimmediate_operand")))] "TARGET_AVX512F" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") (define_insn "*<code><mode>3<mask_name>" - [(set (match_operand:VF_128_256 0 "register_operand" "=x,x,v,v") - (any_logic:VF_128_256 - (match_operand:VF_128_256 1 "vector_operand" "%0,x,v,v") - (match_operand:VF_128_256 2 "vector_operand" "xBm,xm,vm,vm")))] + [(set (match_operand:VFB_128_256 0 "register_operand" "=x,x,v,v") + (any_logic:VFB_128_256 + (match_operand:VFB_128_256 1 "vector_operand" "%0,x,v,v") + (match_operand:VFB_128_256 2 "vector_operand" "xBm,xm,vm,vm")))] "TARGET_SSE && <mask_avx512vl_condition> && !(MEM_P (operands[1]) && MEM_P (operands[2]))" { @@ -4036,6 +4059,8 @@ (define_insn "*<code><mode>3<mask_name>" switch (get_attr_mode (insn)) { + case MODE_V16HF: + case MODE_V8HF: case MODE_V8SF: case MODE_V4SF: suffix = "ps"; @@ -4074,10 +4099,10 @@ (define_insn "*<code><mode>3<mask_name>" (const_string "<MODE>")))]) (define_insn "*<code><mode>3<mask_name>" - [(set (match_operand:VF_512 0 "register_operand" "=v") - (any_logic:VF_512 - (match_operand:VF_512 1 "nonimmediate_operand" "%v") - (match_operand:VF_512 2 "nonimmediate_operand" "vm")))] + [(set (match_operand:VFB_512 0 "register_operand" "=v") + (any_logic:VFB_512 + (match_operand:VFB_512 1 "nonimmediate_operand" "%v") + (match_operand:VFB_512 2 "nonimmediate_operand" "vm")))] "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))" { char buf[128]; @@ -4087,8 +4112,9 @@ (define_insn "*<code><mode>3<mask_name>" suffix = "<ssemodesuffix>"; ops = ""; - /* There is no v<logic>p[sd] in avx512f. Use vp<logic>[dq]. */ - if (!TARGET_AVX512DQ) + /* Since there are no v<logic>p[sd] without AVX512DQ nor v<logic>ph, + use vp<logic>[dq]. */ + if (!TARGET_AVX512DQ || <MODE>mode == V32HFmode) { suffix = GET_MODE_INNER (<MODE>mode) == DFmode ? "q" : "d"; ops = "p"; @@ -4109,14 +4135,14 @@ (define_insn "*<code><mode>3<mask_name>" (define_expand "copysign<mode>3" [(set (match_dup 4) - (and:VF - (not:VF (match_dup 3)) - (match_operand:VF 1 "vector_operand"))) + (and:VFB + (not:VFB (match_dup 3)) + (match_operand:VFB 1 "vector_operand"))) (set (match_dup 5) - (and:VF (match_dup 3) - (match_operand:VF 2 "vector_operand"))) - (set (match_operand:VF 0 "register_operand") - (ior:VF (match_dup 4) (match_dup 5)))] + (and:VFB (match_dup 3) + (match_operand:VFB 2 "vector_operand"))) + (set (match_operand:VFB 0 "register_operand") + (ior:VFB (match_dup 4) (match_dup 5)))] "TARGET_SSE" { operands[3] = ix86_build_signbit_mask (<MODE>mode, 1, 0); @@ -4127,11 +4153,11 @@ (define_expand "copysign<mode>3" (define_expand "xorsign<mode>3" [(set (match_dup 4) - (and:VF (match_dup 3) - (match_operand:VF 2 "vector_operand"))) - (set (match_operand:VF 0 "register_operand") - (xor:VF (match_dup 4) - (match_operand:VF 1 "vector_operand")))] + (and:VFB (match_dup 3) + (match_operand:VFB 2 "vector_operand"))) + (set (match_operand:VFB 0 "register_operand") + (xor:VFB (match_dup 4) + (match_operand:VFB 1 "vector_operand")))] "TARGET_SSE" { operands[3] = ix86_build_signbit_mask (<MODE>mode, 1, 0);
From: "H.J. Lu" <hjl.tools@gmail.com> 1. FP16 vector xor/ior/and/andnot/abs/neg 2. FP16 scalar abs/neg/copysign/xorsign gcc/ChangeLog: * config/i386/i386-expand.c (ix86_expand_fp_absneg_operator): Handle HFmode. (ix86_expand_copysign): Ditto. (ix86_expand_xorsign): Ditto. * config/i386/i386.c (ix86_build_const_vector): Handle HF vector modes. (ix86_build_signbit_mask): Ditto. (ix86_can_change_mode_class): Ditto. * config/i386/i386.md (SSEMODEF): Add HF mode. (ssevecmodef): Ditto. (<code><mode>2): Use MODEFH. (*<code><mode>2_1): Ditto. (define_split): Ditto. (xorsign<mode>3): Ditto. (@xorsign<mode>3_1): Ditto. * config/i386/sse.md (VFB): New mode iterator. (VFB_128_256): Ditto. (VFB_512): Ditto. (sseintvecmode2): Support HF vector mode. (<code><mode>2): Use new mode iterator. (*<code><mode>2): Ditto. (copysign<mode>3): Ditto. (xorsign<mode>3): Ditto. (<code><mode>3<mask_name>): Ditto. (<code><mode>3<mask_name>): Ditto. (<sse>_andnot<mode>3<mask_name>): Adjust for HF vector mode. (<sse>_andnot<mode>3<mask_name>): Ditto. (*<code><mode>3<mask_name>): Ditto. (*<code><mode>3<mask_name>): Ditto. --- gcc/config/i386/i386-expand.c | 12 +++- gcc/config/i386/i386.c | 12 +++- gcc/config/i386/i386.md | 40 ++++++----- gcc/config/i386/sse.md | 128 ++++++++++++++++++++-------------- 4 files changed, 118 insertions(+), 74 deletions(-)