[33/62] AVX512FP16: Add testcase for vcvttph2w/vcvttph2uw/vcvttph2dq/vcvttph2udq/vcvttph2qq/vcvttph2uqq.

diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2dq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2dq-1a.c
new file mode 100644
index 00000000000..0e44aaf1bb5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2dq-1a.c
@@ -0,0 +1,24 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vcvttph2dq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */
+/* { dg-final { scan-assembler-times "vcvttph2dq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2dq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2dq\[ \\t\]+\{sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2dq\[ \\t\]+\{sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i res, res1, res2;
+volatile __m256h x1, x2, x3;
+volatile __mmask16 m16;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvttph_epi32 (x1);
+  res1 = _mm512_mask_cvttph_epi32 (res, m16, x2);
+  res2 = _mm512_maskz_cvttph_epi32 (m16, x3);
+  res = _mm512_cvtt_roundph_epi32 (x1, 4);
+  res1 = _mm512_mask_cvtt_roundph_epi32 (res, m16, x2, 8);
+  res2 = _mm512_maskz_cvtt_roundph_epi32 (m16, x3, 8);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2dq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2dq-1b.c
new file mode 100644
index 00000000000..c18fefbf206
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2dq-1b.c
@@ -0,0 +1,79 @@ 
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */
+
+
+#define AVX512FP16
+#include "avx512fp16-helper.h"
+
+#define N_ELEMS (AVX512F_LEN / 16)
+
+void NOINLINE
+EMULATE(cvtph2_d) (V512 * dest, V512 op1,
+		 __mmask32 k, int zero_mask)
+{
+  V512 v1, v2, v3, v4, v5, v6, v7, v8;
+  int i;
+  __mmask16 m1, m2;
+
+  m1 = k & 0xffff;
+
+  unpack_ph_2twops(op1, &v1, &v2);
+
+  for (i = 0; i < 16; i++) {
+    if (((1 << i) & m1) == 0) {
+      if (zero_mask) {
+	v5.u32[i] = 0;
+      }
+      else {
+	v5.u32[i] = dest->u32[i];
+      }
+    }
+    else {
+      v5.u32[i] = v1.f32[i];
+
+    }
+  }
+  *dest = v5;
+}
+
+void
+TEST (void)
+{
+  V512 res;
+  V512 exp;
+
+  init_src();
+
+  EMULATE(cvtph2_d)(&exp, src1,  NET_MASK, 0);
+  SI(res) = INTRINSIC (_cvttph_epi32) (H_HF(src1));
+  CHECK_RESULT (&res, &exp, N_ELEMS, _cvttph_epi32);
+
+  init_dest(&res, &exp);
+  EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 0);
+  SI(res) = INTRINSIC (_mask_cvttph_epi32) (SI(res), HALF_MASK, H_HF(src1));
+  CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvttph_epi32);
+
+  EMULATE(cvtph2_d)(&exp, src1,  HALF_MASK, 1);
+  SI(res) = INTRINSIC (_maskz_cvttph_epi32) (HALF_MASK, H_HF(src1));
+  CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvttph_epi32);
+
+#if AVX512F_LEN == 512
+  EMULATE(cvtph2_d)(&exp, src1,  NET_MASK, 0);
+  SI(res) = INTRINSIC (_cvtt_roundph_epi32) (H_HF(src1), _ROUND_NINT);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _cvtt_roundph_epi32);
+
+  init_dest(&res, &exp);
+  EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 0);
+  SI(res) = INTRINSIC (_mask_cvtt_roundph_epi32) (SI(res), HALF_MASK, H_HF(src1), _ROUND_NINT);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtt_roundph_epi32);
+
+  EMULATE(cvtph2_d)(&exp, src1,  HALF_MASK, 1);
+  SI(res) = INTRINSIC (_maskz_cvtt_roundph_epi32) (HALF_MASK, H_HF(src1), _ROUND_NINT);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtt_roundph_epi32);
+#endif
+
+  if (n_errs != 0)
+    abort ();
+}
+
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2qq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2qq-1a.c
new file mode 100644
index 00000000000..124169467ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2qq-1a.c
@@ -0,0 +1,24 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vcvttph2qq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */
+/* { dg-final { scan-assembler-times "vcvttph2qq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2qq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2qq\[ \\t\]+\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2qq\[ \\t\]+\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i res, res1, res2;
+volatile __m128h x1, x2, x3;
+volatile __mmask8 m8;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvttph_epi64 (x1);
+  res1 = _mm512_mask_cvttph_epi64 (res, m8, x2);
+  res2 = _mm512_maskz_cvttph_epi64 (m8, x3);
+  res = _mm512_cvtt_roundph_epi64 (x1, 4);
+  res1 = _mm512_mask_cvtt_roundph_epi64 (res, m8, x2, 8);
+  res2 = _mm512_maskz_cvtt_roundph_epi64 (m8, x3, 8);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2qq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2qq-1b.c
new file mode 100644
index 00000000000..2a9a2ca26f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2qq-1b.c
@@ -0,0 +1,78 @@ 
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */
+
+
+#define AVX512FP16
+#include "avx512fp16-helper.h"
+
+#define N_ELEMS (AVX512F_LEN / 16)
+
+void NOINLINE
+EMULATE(cvtph2_q) (V512 * dest, V512 op1,
+		 __mmask32 k, int zero_mask)
+{
+  V512 v1, v2, v3, v4, v5, v6, v7, v8;
+  int i;
+  __mmask16 m1, m2;
+
+  m1 = k & 0xffff;
+
+  unpack_ph_2twops(op1, &v1, &v2);
+
+  for (i = 0; i < 8; i++) {
+    if (((1 << i) & m1) == 0) {
+      if (zero_mask) {
+	v5.u64[i] = 0;
+      }
+      else {
+	v5.u64[i] = dest->u64[i];
+      }
+    }
+    else {
+      v5.u64[i] = v1.f32[i];
+    }
+  }
+  *dest = v5;
+}
+
+void
+TEST (void)
+{
+  V512 res;
+  V512 exp;
+
+  init_src();
+
+  EMULATE(cvtph2_q)(&exp, src1,  NET_MASK, 0);
+  SI(res) = INTRINSIC (_cvttph_epi64) (src1.xmmh[0]);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _cvttph_epi64);
+
+  init_dest(&res, &exp);
+  EMULATE(cvtph2_q)(&exp, src1, 0xcc, 0);
+  SI(res) = INTRINSIC (_mask_cvttph_epi64) (SI(res), 0xcc, src1.xmmh[0]);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvttph_epi64);
+
+  EMULATE(cvtph2_q)(&exp, src1,  0xfa, 1);
+  SI(res) = INTRINSIC (_maskz_cvttph_epi64) (0xfa, src1.xmmh[0]);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvttph_epi64);
+
+#if AVX512F_LEN == 512
+  EMULATE(cvtph2_q)(&exp, src1,  NET_MASK, 0);
+  SI(res) = INTRINSIC (_cvtt_roundph_epi64) (src1.xmmh[0], _ROUND_NINT);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _cvtt_roundph_epi64);
+
+  init_dest(&res, &exp);
+  EMULATE(cvtph2_q)(&exp, src1, 0xcc, 0);
+  SI(res) = INTRINSIC (_mask_cvtt_roundph_epi64) (SI(res), 0xcc, src1.xmmh[0], _ROUND_NINT);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtt_roundph_epi64);
+
+  EMULATE(cvtph2_q)(&exp, src1,  0xfa, 1);
+  SI(res) = INTRINSIC (_maskz_cvtt_roundph_epi64) (0xfa, src1.xmmh[0], _ROUND_NINT);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtt_roundph_epi64);
+#endif
+
+  if (n_errs != 0) {
+      abort ();
+  }
+}
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2udq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2udq-1a.c
new file mode 100644
index 00000000000..0fd60f56777
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2udq-1a.c
@@ -0,0 +1,24 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vcvttph2udq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */
+/* { dg-final { scan-assembler-times "vcvttph2udq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2udq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2udq\[ \\t\]+\{sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2udq\[ \\t\]+\{sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i res, res1, res2;
+volatile __m256h x1, x2, x3;
+volatile __mmask16 m16;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvttph_epu32 (x1);
+  res1 = _mm512_mask_cvttph_epu32 (res, m16, x2);
+  res2 = _mm512_maskz_cvttph_epu32 (m16, x3);
+  res = _mm512_cvtt_roundph_epu32 (x1, 4);
+  res1 = _mm512_mask_cvtt_roundph_epu32 (res, m16, x2, 8);
+  res2 = _mm512_maskz_cvtt_roundph_epu32 (m16, x3, 8);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2udq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2udq-1b.c
new file mode 100644
index 00000000000..98bce374753
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2udq-1b.c
@@ -0,0 +1,79 @@ 
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */
+
+
+#define AVX512FP16
+#include "avx512fp16-helper.h"
+
+#define N_ELEMS (AVX512F_LEN / 16)
+
+void NOINLINE
+EMULATE(cvtph2_d) (V512 * dest, V512 op1,
+		 __mmask32 k, int zero_mask)
+{
+  V512 v1, v2, v3, v4, v5, v6, v7, v8;
+  int i;
+  __mmask16 m1, m2;
+
+  m1 = k & 0xffff;
+
+  unpack_ph_2twops(op1, &v1, &v2);
+
+  for (i = 0; i < 16; i++) {
+    if (((1 << i) & m1) == 0) {
+      if (zero_mask) {
+	v5.u32[i] = 0;
+      }
+      else {
+	v5.u32[i] = dest->u32[i];
+      }
+    }
+    else {
+      v5.u32[i] = v1.f32[i];
+
+    }
+  }
+  *dest = v5;
+}
+
+void
+TEST (void)
+{
+  V512 res;
+  V512 exp;
+
+  init_src();
+
+  EMULATE(cvtph2_d)(&exp, src1,  NET_MASK, 0);
+  SI(res) = INTRINSIC (_cvttph_epu32) (H_HF(src1));
+  CHECK_RESULT (&res, &exp, N_ELEMS, _cvttph_epu32);
+
+  init_dest(&res, &exp);
+  EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 0);
+  SI(res) = INTRINSIC (_mask_cvttph_epu32) (SI(res), HALF_MASK, H_HF(src1));
+  CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvttph_epu32);
+
+  EMULATE(cvtph2_d)(&exp, src1,  HALF_MASK, 1);
+  SI(res) = INTRINSIC (_maskz_cvttph_epu32) (HALF_MASK, H_HF(src1));
+  CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvttph_epu32);
+
+#if AVX512F_LEN == 512
+  EMULATE(cvtph2_d)(&exp, src1,  NET_MASK, 0);
+  SI(res) = INTRINSIC (_cvtt_roundph_epu32) (H_HF(src1), _ROUND_NINT);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _cvtt_roundph_epu32);
+
+  init_dest(&res, &exp);
+  EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 0);
+  SI(res) = INTRINSIC (_mask_cvtt_roundph_epu32) (SI(res), HALF_MASK, H_HF(src1), _ROUND_NINT);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtt_roundph_epu32);
+
+  EMULATE(cvtph2_d)(&exp, src1,  HALF_MASK, 1);
+  SI(res) = INTRINSIC (_maskz_cvtt_roundph_epu32) (HALF_MASK, H_HF(src1), _ROUND_NINT);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtt_roundph_epu32);
+#endif
+
+  if (n_errs != 0) {
+      abort ();
+  }
+}
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uqq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uqq-1a.c
new file mode 100644
index 00000000000..04fee2936c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uqq-1a.c
@@ -0,0 +1,24 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vcvttph2uqq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */
+/* { dg-final { scan-assembler-times "vcvttph2uqq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2uqq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2uqq\[ \\t\]+\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2uqq\[ \\t\]+\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i res, res1, res2;
+volatile __m128h x1, x2, x3;
+volatile __mmask8 m8;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvttph_epu64 (x1);
+  res1 = _mm512_mask_cvttph_epu64 (res, m8, x2);
+  res2 = _mm512_maskz_cvttph_epu64 (m8, x3);
+  res = _mm512_cvtt_roundph_epu64 (x1, 4);
+  res1 = _mm512_mask_cvtt_roundph_epu64 (res, m8, x2, 8);
+  res2 = _mm512_maskz_cvtt_roundph_epu64 (m8, x3, 8);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uqq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uqq-1b.c
new file mode 100644
index 00000000000..31879ef8983
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uqq-1b.c
@@ -0,0 +1,78 @@ 
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */
+
+
+#define AVX512FP16
+#include "avx512fp16-helper.h"
+
+#define N_ELEMS (AVX512F_LEN / 16)
+
+void NOINLINE
+EMULATE(cvtph2_q) (V512 * dest, V512 op1,
+		 __mmask32 k, int zero_mask)
+{
+  V512 v1, v2, v3, v4, v5, v6, v7, v8;
+  int i;
+  __mmask16 m1, m2;
+
+  m1 = k & 0xffff;
+
+  unpack_ph_2twops(op1, &v1, &v2);
+
+  for (i = 0; i < 8; i++) {
+    if (((1 << i) & m1) == 0) {
+      if (zero_mask) {
+	v5.u64[i] = 0;
+      }
+      else {
+	v5.u64[i] = dest->u64[i];
+      }
+    }
+    else {
+      v5.u64[i] = v1.f32[i];
+    }
+  }
+  *dest = v5;
+}
+
+void
+TEST (void)
+{
+  V512 res;
+  V512 exp;
+
+  init_src();
+
+  EMULATE(cvtph2_q)(&exp, src1,  NET_MASK, 0);
+  SI(res) = INTRINSIC (_cvttph_epu64) (src1.xmmh[0]);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _cvttph_epu64);
+
+  init_dest(&res, &exp);
+  EMULATE(cvtph2_q)(&exp, src1, 0xcc, 0);
+  SI(res) = INTRINSIC (_mask_cvttph_epu64) (SI(res), 0xcc, src1.xmmh[0]);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvttph_epu64);
+
+  EMULATE(cvtph2_q)(&exp, src1,  0xfc, 1);
+  SI(res) = INTRINSIC (_maskz_cvttph_epu64) (0xfc, src1.xmmh[0]);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvttph_epu64);
+
+#if AVX512F_LEN == 512
+  EMULATE(cvtph2_q)(&exp, src1,  NET_MASK, 0);
+  SI(res) = INTRINSIC (_cvtt_roundph_epu64) (src1.xmmh[0], _ROUND_NINT);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _cvtt_roundph_epu64);
+
+  init_dest(&res, &exp);
+  EMULATE(cvtph2_q)(&exp, src1, 0xcc, 0);
+  SI(res) = INTRINSIC (_mask_cvtt_roundph_epu64) (SI(res), 0xcc, src1.xmmh[0], _ROUND_NINT);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtt_roundph_epu64);
+
+  EMULATE(cvtph2_q)(&exp, src1,  0xfc, 1);
+  SI(res) = INTRINSIC (_maskz_cvtt_roundph_epu64) (0xfc, src1.xmmh[0], _ROUND_NINT);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtt_roundph_epu64);
+#endif
+
+  if (n_errs != 0) {
+      abort ();
+  }
+}
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uw-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uw-1a.c
new file mode 100644
index 00000000000..b31af8441a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uw-1a.c
@@ -0,0 +1,24 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vcvttph2uw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */
+/* { dg-final { scan-assembler-times "vcvttph2uw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2uw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2uw\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2uw\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i res, res1, res2;
+volatile __m512h x1, x2, x3;
+volatile __mmask32 m32;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvttph_epu16 (x1);
+  res1 = _mm512_mask_cvttph_epu16 (res, m32, x2);
+  res2 = _mm512_maskz_cvttph_epu16 (m32, x3);
+  res = _mm512_cvtt_roundph_epu16 (x1, 4);
+  res1 = _mm512_mask_cvtt_roundph_epu16 (res, m32, x2, 8);
+  res2 = _mm512_maskz_cvtt_roundph_epu16 (m32, x3, 8);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uw-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uw-1b.c
new file mode 100644
index 00000000000..34e94e8e549
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2uw-1b.c
@@ -0,0 +1,84 @@ 
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */
+
+
+#define AVX512FP16
+#include "avx512fp16-helper.h"
+
+#define N_ELEMS (AVX512F_LEN / 16)
+
+void NOINLINE
+EMULATE(cvtph2_w) (V512 * dest, V512 op1,
+		 __mmask32 k, int zero_mask)
+{
+  V512 v1, v2, v3, v4, v5, v6, v7, v8;
+  int i;
+  __mmask16 m1, m2;
+
+  m1 = k & 0xffff;
+  m2 = (k >> 16) & 0xffff;
+
+  unpack_ph_2twops(op1, &v1, &v2);
+
+  for (i = 0; i < 16; i++) {
+    if (((1 << i) & m1) == 0) {
+      if (zero_mask) {
+	dest->u16[i] = 0;
+      }
+    }
+    else {
+      dest->u16[i] = v1.f32[i];
+
+    }
+
+    if (((1 << i) & m2) == 0) {
+      if (zero_mask) {
+	dest->u16[i+16] = 0;
+      }
+    }
+    else {
+      dest->u16[i+16] = v2.f32[i];
+    }
+  }
+}
+
+void
+TEST (void)
+{
+  V512 res;
+  V512 exp;
+
+  init_src();
+
+  EMULATE(cvtph2_w)(&exp, src1,  NET_MASK, 0);
+  SI(res) = INTRINSIC (_cvttph_epu16) (HF(src1));
+  CHECK_RESULT (&res, &exp, N_ELEMS, _cvttph_epu16);
+
+  init_dest(&res, &exp);
+  EMULATE(cvtph2_w)(&exp, src1, MASK_VALUE, 0);
+  SI(res) = INTRINSIC (_mask_cvttph_epu16) (SI(res), MASK_VALUE, HF(src1));
+  CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvttph_epu16);
+
+  EMULATE(cvtph2_w)(&exp, src1, ZMASK_VALUE, 1);
+  SI(res) = INTRINSIC (_maskz_cvttph_epu16) (ZMASK_VALUE, HF(src1));
+  CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvttph_epu16);
+
+#if AVX512F_LEN == 512
+  EMULATE(cvtph2_w)(&exp, src1,  NET_MASK, 0);
+  SI(res) = INTRINSIC (_cvtt_roundph_epu16) (HF(src1), _ROUND_NINT);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _cvtt_roundph_epu16);
+
+  init_dest(&res, &exp);
+  EMULATE(cvtph2_w)(&exp, src1, MASK_VALUE, 0);
+  SI(res) = INTRINSIC (_mask_cvtt_roundph_epu16) (SI(res), MASK_VALUE, HF(src1), _ROUND_NINT);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtt_roundph_epu16);
+
+  EMULATE(cvtph2_w)(&exp, src1, ZMASK_VALUE, 1);
+  SI(res) = INTRINSIC (_maskz_cvtt_roundph_epu16) (ZMASK_VALUE, HF(src1), _ROUND_NINT);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtt_roundph_epu16);
+#endif
+
+  if (n_errs != 0)
+    abort ();
+}
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2w-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2w-1a.c
new file mode 100644
index 00000000000..a918594d0d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2w-1a.c
@@ -0,0 +1,24 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vcvttph2w\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */
+/* { dg-final { scan-assembler-times "vcvttph2w\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2w\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2w\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2w\[ \\t\]+\{sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i res, res1, res2;
+volatile __m512h x1, x2, x3;
+volatile __mmask32 m32;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvttph_epi16 (x1);
+  res1 = _mm512_mask_cvttph_epi16 (res, m32, x2);
+  res2 = _mm512_maskz_cvttph_epi16 (m32, x3);
+  res = _mm512_cvtt_roundph_epi16 (x1, 4);
+  res1 = _mm512_mask_cvtt_roundph_epi16 (res, m32, x2, 8);
+  res2 = _mm512_maskz_cvtt_roundph_epi16 (m32, x3, 8);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2w-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2w-1b.c
new file mode 100644
index 00000000000..23bc8e680c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvttph2w-1b.c
@@ -0,0 +1,83 @@ 
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */
+
+#define AVX512FP16
+#include "avx512fp16-helper.h"
+
+#define N_ELEMS (AVX512F_LEN / 16)
+
+void NOINLINE
+EMULATE(cvtph2_w) (V512 * dest, V512 op1,
+		 __mmask32 k, int zero_mask)
+{
+  V512 v1, v2, v3, v4, v5, v6, v7, v8;
+  int i;
+  __mmask16 m1, m2;
+
+  m1 = k & 0xffff;
+  m2 = (k >> 16) & 0xffff;
+
+  unpack_ph_2twops(op1, &v1, &v2);
+
+  for (i = 0; i < 16; i++) {
+    if (((1 << i) & m1) == 0) {
+      if (zero_mask) {
+	dest->u16[i] = 0;
+      }
+    }
+    else {
+      dest->u16[i] = v1.f32[i];
+
+    }
+
+    if (((1 << i) & m2) == 0) {
+      if (zero_mask) {
+	dest->u16[i+16] = 0;
+      }
+    }
+    else {
+      dest->u16[i+16] = v2.f32[i];
+    }
+  }
+}
+
+void
+TEST (void)
+{
+  V512 res, exp;
+
+  init_src();
+
+  EMULATE(cvtph2_w)(&exp, src1,  NET_MASK, 0);
+  SI(res) = INTRINSIC (_cvttph_epi16) (HF(src1));
+  CHECK_RESULT (&res, &exp, N_ELEMS, _cvttph_epi16);
+
+  init_dest(&res, &exp);
+  EMULATE(cvtph2_w)(&exp, src1, MASK_VALUE, 0);
+  SI(res) = INTRINSIC (_mask_cvttph_epi16) (SI(res), MASK_VALUE, HF(src1));
+  CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvttph_epi16);
+
+  EMULATE(cvtph2_w)(&exp, src1,  ZMASK_VALUE, 1);
+  SI(res) = INTRINSIC (_maskz_cvttph_epi16) (ZMASK_VALUE, HF(src1));
+  CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvttph_epi16);
+
+#if AVX512F_LEN == 512
+  EMULATE(cvtph2_w)(&exp, src1,  NET_MASK, 0);
+  SI(res) = INTRINSIC (_cvtt_roundph_epi16) (HF(src1), _ROUND_NINT);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _cvtt_roundph_epi16);
+
+  init_dest(&res, &exp);
+  EMULATE(cvtph2_w)(&exp, src1, MASK_VALUE, 0);
+  SI(res) = INTRINSIC (_mask_cvtt_roundph_epi16) (SI(res), MASK_VALUE, HF(src1), _ROUND_NINT);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtt_roundph_epi16);
+
+  EMULATE(cvtph2_w)(&exp, src1,  ZMASK_VALUE, 1);
+  SI(res) = INTRINSIC (_maskz_cvtt_roundph_epi16) (ZMASK_VALUE, HF(src1), _ROUND_NINT);
+  CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtt_roundph_epi16);
+#endif
+
+  if (n_errs != 0) {
+      abort ();
+  }
+}
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2dq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2dq-1a.c
new file mode 100644
index 00000000000..b4c084020ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2dq-1a.c
@@ -0,0 +1,27 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vcvttph2dq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2dq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2dq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2dq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2dq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2dq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256i res1;
+volatile __m128i res2;
+volatile __m128h x3;
+volatile __mmask8 m8;
+
+void extern
+avx512f_test (void)
+{
+  res1 = _mm256_cvttph_epi32 (x3);
+  res1 = _mm256_mask_cvttph_epi32 (res1, m8, x3);
+  res1 = _mm256_maskz_cvttph_epi32 (m8, x3);
+
+  res2 = _mm_cvttph_epi32 (x3);
+  res2 = _mm_mask_cvttph_epi32 (res2, m8, x3);
+  res2 = _mm_maskz_cvttph_epi32 (m8, x3);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2dq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2dq-1b.c
new file mode 100644
index 00000000000..f9d82f92f4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2dq-1b.c
@@ -0,0 +1,15 @@ 
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */
+
+#define AVX512VL
+#define AVX512F_LEN 256      
+#define AVX512F_LEN_HALF 128 
+#include "avx512fp16-vcvttph2dq-1b.c"
+                             
+#undef AVX512F_LEN           
+#undef AVX512F_LEN_HALF      
+                             
+#define AVX512F_LEN 128      
+#define AVX512F_LEN_HALF 128 
+#include "avx512fp16-vcvttph2dq-1b.c"
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2qq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2qq-1a.c
new file mode 100644
index 00000000000..421c688ee29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2qq-1a.c
@@ -0,0 +1,27 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vcvttph2qq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2qq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2qq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2qq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2qq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2qq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256i res1;
+volatile __m128i res2;
+volatile __m128h x3;
+volatile __mmask8 m8;
+
+void extern
+avx512f_test (void)
+{
+  res1 = _mm256_cvttph_epi64 (x3);
+  res1 = _mm256_mask_cvttph_epi64 (res1, m8, x3);
+  res1 = _mm256_maskz_cvttph_epi64 (m8, x3);
+
+  res2 = _mm_cvttph_epi64 (x3);
+  res2 = _mm_mask_cvttph_epi64 (res2, m8, x3);
+  res2 = _mm_maskz_cvttph_epi64 (m8, x3);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2qq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2qq-1b.c
new file mode 100644
index 00000000000..323ab74fa05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2qq-1b.c
@@ -0,0 +1,15 @@ 
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */
+
+#define AVX512VL
+#define AVX512F_LEN 256      
+#define AVX512F_LEN_HALF 128 
+#include "avx512fp16-vcvttph2qq-1b.c"
+                             
+#undef AVX512F_LEN           
+#undef AVX512F_LEN_HALF      
+                             
+#define AVX512F_LEN 128      
+#define AVX512F_LEN_HALF 128 
+#include "avx512fp16-vcvttph2qq-1b.c"
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2udq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2udq-1a.c
new file mode 100644
index 00000000000..60f43189d61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2udq-1a.c
@@ -0,0 +1,27 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vcvttph2udq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2udq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2udq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2udq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2udq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2udq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256i res1;
+volatile __m128i res2;
+volatile __m128h x3;
+volatile __mmask8 m8;
+
+void extern
+avx512f_test (void)
+{
+  res1 = _mm256_cvttph_epu32 (x3);
+  res1 = _mm256_mask_cvttph_epu32 (res1, m8, x3);
+  res1 = _mm256_maskz_cvttph_epu32 (m8, x3);
+
+  res2 = _mm_cvttph_epu32 (x3);
+  res2 = _mm_mask_cvttph_epu32 (res2, m8, x3);
+  res2 = _mm_maskz_cvttph_epu32 (m8, x3);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2udq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2udq-1b.c
new file mode 100644
index 00000000000..61365d456c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2udq-1b.c
@@ -0,0 +1,15 @@ 
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */
+
+#define AVX512VL
+#define AVX512F_LEN 256      
+#define AVX512F_LEN_HALF 128 
+#include "avx512fp16-vcvttph2udq-1b.c"
+                             
+#undef AVX512F_LEN           
+#undef AVX512F_LEN_HALF      
+                             
+#define AVX512F_LEN 128      
+#define AVX512F_LEN_HALF 128 
+#include "avx512fp16-vcvttph2udq-1b.c"
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uqq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uqq-1a.c
new file mode 100644
index 00000000000..37008f9d9e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uqq-1a.c
@@ -0,0 +1,27 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vcvttph2uqq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2uqq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2uqq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2uqq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2uqq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2uqq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256i res1;
+volatile __m128i res2;
+volatile __m128h x3;
+volatile __mmask8 m8;
+
+void extern
+avx512f_test (void)
+{
+  res1 = _mm256_cvttph_epu64 (x3);
+  res1 = _mm256_mask_cvttph_epu64 (res1, m8, x3);
+  res1 = _mm256_maskz_cvttph_epu64 (m8, x3);
+
+  res2 = _mm_cvttph_epu64 (x3);
+  res2 = _mm_mask_cvttph_epu64 (res2, m8, x3);
+  res2 = _mm_maskz_cvttph_epu64 (m8, x3);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uqq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uqq-1b.c
new file mode 100644
index 00000000000..6360402e6d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uqq-1b.c
@@ -0,0 +1,15 @@ 
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */
+
+#define AVX512VL
+#define AVX512F_LEN 256      
+#define AVX512F_LEN_HALF 128 
+#include "avx512fp16-vcvttph2uqq-1b.c"
+                             
+#undef AVX512F_LEN           
+#undef AVX512F_LEN_HALF      
+                             
+#define AVX512F_LEN 128      
+#define AVX512F_LEN_HALF 128 
+#include "avx512fp16-vcvttph2uqq-1b.c"
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uw-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uw-1a.c
new file mode 100644
index 00000000000..eafa31a786b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uw-1a.c
@@ -0,0 +1,29 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vcvttph2uw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2uw\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2uw\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2uw\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2uw\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2uw\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256i res1;
+volatile __m128i res2;
+volatile __m256h x3;
+volatile __m128h x4;
+volatile __mmask16 m16;
+volatile __mmask8 m8;
+
+void extern
+avx512f_test (void)
+{
+  res1 = _mm256_cvttph_epu16 (x3);
+  res1 = _mm256_mask_cvttph_epu16 (res1, m16, x3);
+  res1 = _mm256_maskz_cvttph_epu16 (m16, x3);
+
+  res2 = _mm_cvttph_epu16 (x4);
+  res2 = _mm_mask_cvttph_epu16 (res2, m8, x4);
+  res2 = _mm_maskz_cvttph_epu16 (m8, x4);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uw-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uw-1b.c
new file mode 100644
index 00000000000..dd5ed9d5b38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2uw-1b.c
@@ -0,0 +1,15 @@ 
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */
+
+#define AVX512VL
+#define AVX512F_LEN 256      
+#define AVX512F_LEN_HALF 128 
+#include "avx512fp16-vcvttph2uw-1b.c"
+                             
+#undef AVX512F_LEN           
+#undef AVX512F_LEN_HALF      
+                             
+#define AVX512F_LEN 128      
+#define AVX512F_LEN_HALF 128 
+#include "avx512fp16-vcvttph2uw-1b.c"
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2w-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2w-1a.c
new file mode 100644
index 00000000000..7476d3c1160
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2w-1a.c
@@ -0,0 +1,29 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vcvttph2w\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2w\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2w\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2w\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2w\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttph2w\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256i res1;
+volatile __m128i res2;
+volatile __m256h x3;
+volatile __m128h x4;
+volatile __mmask16 m16;
+volatile __mmask8 m8;
+
+void extern
+avx512f_test (void)
+{
+  res1 = _mm256_cvttph_epi16 (x3);
+  res1 = _mm256_mask_cvttph_epi16 (res1, m16, x3);
+  res1 = _mm256_maskz_cvttph_epi16 (m16, x3);
+
+  res2 = _mm_cvttph_epi16 (x4);
+  res2 = _mm_mask_cvttph_epi16 (res2, m8, x4);
+  res2 = _mm_maskz_cvttph_epi16 (m8, x4);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2w-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2w-1b.c
new file mode 100644
index 00000000000..7a04a6a8ebc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvttph2w-1b.c
@@ -0,0 +1,15 @@ 
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */
+
+#define AVX512VL
+#define AVX512F_LEN 256      
+#define AVX512F_LEN_HALF 128 
+#include "avx512fp16-vcvttph2w-1b.c"
+                             
+#undef AVX512F_LEN           
+#undef AVX512F_LEN_HALF      
+                             
+#define AVX512F_LEN 128      
+#define AVX512F_LEN_HALF 128 
+#include "avx512fp16-vcvttph2w-1b.c"
+