From patchwork Thu Jul 1 06:16:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 1499370 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=Z8iIZuOf; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GFpny0Qcyz9sX5 for ; Thu, 1 Jul 2021 16:53:25 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1265C383B81D for ; Thu, 1 Jul 2021 06:53:23 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1265C383B81D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1625122403; bh=LvM/bMzZamYaXpiXEqTTetzrq/RRPL9Tl+a9UzPiNwI=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=Z8iIZuOfH+I/I1ReXxiLa03id7MW6/u5iakeQxkKerTreWNhHCORCN9fyASKQBIsW pYLfOHh7S0m9AgGhGqSNDvvqMZllN1PDX4k9uNwAMB8RqnAVWs+qt9Eu6rQHwC4WJQ qaj9lPqwBtlogjLJZFOEQrqUWS7y7r0ZxnNIMqlc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by sourceware.org (Postfix) with ESMTPS id 73D77384841D for ; Thu, 1 Jul 2021 06:17:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 73D77384841D X-IronPort-AV: E=McAfee;i="6200,9189,10031"; a="272334079" X-IronPort-AV: E=Sophos;i="5.83,313,1616482800"; d="scan'208";a="272334079" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2021 23:17:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,313,1616482800"; d="scan'208";a="489821390" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga001.jf.intel.com with ESMTP; 30 Jun 2021 23:17:41 -0700 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.236.50]) by scymds01.sc.intel.com with ESMTP id 1616GmfA031625; Wed, 30 Jun 2021 23:17:40 -0700 To: gcc-patches@gcc.gnu.org Subject: [PATCH 31/62] AVX512FP16: Add testcase for vcvtsh2si/vcvtsh2usi/vcvtsi2sh/vcvtusi2sh. Date: Thu, 1 Jul 2021 14:16:17 +0800 Message-Id: <20210701061648.9447-32-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20210701061648.9447-1-hongtao.liu@intel.com> References: <20210701061648.9447-1-hongtao.liu@intel.com> X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Cc: jakub@redhat.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" gcc/testsuite/ChangeLog: * gcc.target/i386/avx512fp16-helper.h (V512): Add int32 component. * gcc.target/i386/avx512fp16-vcvtsh2si-1a.c: New test. * gcc.target/i386/avx512fp16-vcvtsh2si-1b.c: Ditto. * gcc.target/i386/avx512fp16-vcvtsh2si64-1a.c: Ditto. * gcc.target/i386/avx512fp16-vcvtsh2si64-1b.c: Ditto. * gcc.target/i386/avx512fp16-vcvtsh2usi-1a.c: Ditto. * gcc.target/i386/avx512fp16-vcvtsh2usi-1b.c: Ditto. * gcc.target/i386/avx512fp16-vcvtsh2usi64-1a.c: Ditto. * gcc.target/i386/avx512fp16-vcvtsh2usi64-1b.c: Ditto. * gcc.target/i386/avx512fp16-vcvtsi2sh-1a.c: Ditto. * gcc.target/i386/avx512fp16-vcvtsi2sh-1b.c: Ditto. * gcc.target/i386/avx512fp16-vcvtsi2sh64-1a.c: Ditto. * gcc.target/i386/avx512fp16-vcvtsi2sh64-1b.c: Ditto. * gcc.target/i386/avx512fp16-vcvtusi2sh-1a.c: Ditto. * gcc.target/i386/avx512fp16-vcvtusi2sh-1b.c: Ditto. * gcc.target/i386/avx512fp16-vcvtusi2sh64-1a.c: Ditto. * gcc.target/i386/avx512fp16-vcvtusi2sh64-1b.c: Ditto. --- .../gcc.target/i386/avx512fp16-helper.h | 1 + .../gcc.target/i386/avx512fp16-vcvtsh2si-1a.c | 17 ++++++ .../gcc.target/i386/avx512fp16-vcvtsh2si-1b.c | 54 +++++++++++++++++++ .../i386/avx512fp16-vcvtsh2si64-1a.c | 17 ++++++ .../i386/avx512fp16-vcvtsh2si64-1b.c | 52 ++++++++++++++++++ .../i386/avx512fp16-vcvtsh2usi-1a.c | 17 ++++++ .../i386/avx512fp16-vcvtsh2usi-1b.c | 54 +++++++++++++++++++ .../i386/avx512fp16-vcvtsh2usi64-1a.c | 16 ++++++ .../i386/avx512fp16-vcvtsh2usi64-1b.c | 53 ++++++++++++++++++ .../gcc.target/i386/avx512fp16-vcvtsi2sh-1a.c | 16 ++++++ .../gcc.target/i386/avx512fp16-vcvtsi2sh-1b.c | 41 ++++++++++++++ .../i386/avx512fp16-vcvtsi2sh64-1a.c | 16 ++++++ .../i386/avx512fp16-vcvtsi2sh64-1b.c | 41 ++++++++++++++ .../i386/avx512fp16-vcvtusi2sh-1a.c | 16 ++++++ .../i386/avx512fp16-vcvtusi2sh-1b.c | 41 ++++++++++++++ .../i386/avx512fp16-vcvtusi2sh64-1a.c | 16 ++++++ .../i386/avx512fp16-vcvtusi2sh64-1b.c | 41 ++++++++++++++ 17 files changed, 509 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si-1b.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si64-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si64-1b.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi-1b.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi64-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi64-1b.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh-1b.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh64-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh64-1b.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh-1b.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh64-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh64-1b.c diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-helper.h b/gcc/testsuite/gcc.target/i386/avx512fp16-helper.h index aa83b66998c..cf1c536d9f7 100644 --- a/gcc/testsuite/gcc.target/i386/avx512fp16-helper.h +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-helper.h @@ -34,6 +34,7 @@ typedef union __m128i xmmi[4]; unsigned short u16[32]; unsigned int u32[16]; + int i32[16]; long long s64[8]; unsigned long long u64[8]; float f32[16]; diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si-1a.c new file mode 100644 index 00000000000..f29c953572d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si-1a.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtsh2si\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%eax" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsh2si\[ \\t\]+\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%eax" 1 } } */ + + +#include + +volatile __m128h x1; +volatile int res1; + +void extern +avx512f_test (void) +{ + res1 = _mm_cvtsh_i32 (x1); + res1 = _mm_cvt_roundsh_i32 (x1, 8); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si-1b.c new file mode 100644 index 00000000000..89c492cfc44 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si-1b.c @@ -0,0 +1,54 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 2 + +void NOINLINE +emulate_cvtph2_d(V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u32[i] = 0; + } + else { + v5.u32[i] = dest->u32[i]; + } + } + else { + v5.u32[i] = v1.f32[i]; + + } + } + *dest = v5; +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_cvtph2_d(&exp, src1, NET_MASK, 0); + res.i32[0] = _mm_cvt_roundsh_i32(src1.xmmh[0], _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_cvt_roundsh_i32"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si64-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si64-1a.c new file mode 100644 index 00000000000..0289ebf95ea --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si64-1a.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtsh2si\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%rax" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsh2si\[ \\t\]+\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%rax" 1 } } */ + + +#include + +volatile __m128h x1; +volatile long long res2; + +void extern +avx512f_test (void) +{ + res2 = _mm_cvtsh_i64 (x1); + res2 = _mm_cvt_roundsh_i64 (x1, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si64-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si64-1b.c new file mode 100644 index 00000000000..6a5e836fd7f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2si64-1b.c @@ -0,0 +1,52 @@ +/* { dg-do run { target { { ! ia32 } && avx512fp16 } } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 4 + +void NOINLINE +emulate_cvtph2_q(V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 8; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u64[i] = 0; + } + else { + v5.u64[i] = dest->u64[i]; + } + } + else { + v5.u64[i] = v1.f32[i]; + } + } + *dest = v5; +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_cvtph2_q(&exp, src1, NET_MASK, 0); + res.s64[0] = _mm_cvt_roundsh_i64(src1.xmmh[0], _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_cvt_roundsh_i64"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi-1a.c new file mode 100644 index 00000000000..7d00867247e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi-1a.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtsh2usi\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%eax" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsh2usi\[ \\t\]+\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%eax" 1 } } */ + + +#include + +volatile __m128h x1; +volatile unsigned int res1; + +void extern +avx512f_test (void) +{ + res1 = _mm_cvtsh_u32 (x1); + res1 = _mm_cvt_roundsh_u32 (x1, 8); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi-1b.c new file mode 100644 index 00000000000..466ce6ead83 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi-1b.c @@ -0,0 +1,54 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 2 + +void NOINLINE +emulate_cvtph2_d(V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u32[i] = 0; + } + else { + v5.u32[i] = dest->u32[i]; + } + } + else { + v5.u32[i] = v1.f32[i]; + + } + } + *dest = v5; +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_cvtph2_d(&exp, src1, NET_MASK, 0); + res.u32[0] = _mm_cvt_roundsh_i32(src1.xmmh[0], _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_cvt_roundsh_u32"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi64-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi64-1a.c new file mode 100644 index 00000000000..363252d8d5d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi64-1a.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mavx512fp16 -O2 " } */ +/* { dg-final { scan-assembler-times "vcvtsh2usi\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%rax" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsh2usi\[ \\t\]+\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%rax" 1 } } */ + +#include + +volatile __m128h x1; +volatile unsigned long long res2; + +void extern +avx512f_test (void) +{ + res2 = _mm_cvtsh_u64 (x1); + res2 = _mm_cvt_roundsh_u64 (x1, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi64-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi64-1b.c new file mode 100644 index 00000000000..74643ae2bd6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsh2usi64-1b.c @@ -0,0 +1,53 @@ +/* { dg-do run { target { { ! ia32 } && avx512fp16 } } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 4 + +void NOINLINE +emulate_cvtph2_q(V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 8; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u64[i] = 0; + } + else { + v5.u64[i] = dest->u64[i]; + } + } + else { + v5.u64[i] = v1.f32[i]; + } + } + *dest = v5; +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_cvtph2_q(&exp, src1, NET_MASK, 0); + res.u64[0] = _mm_cvt_roundsh_i64(src1.xmmh[0], _ROUND_NINT); + check_results(&res, &exp, 4, "_mm_cvt_roundsh_u64"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh-1a.c new file mode 100644 index 00000000000..4cd69d9b4e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh-1a.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtsi2sh\[ \\t\]+\[^%\n\]*%e\[^\{\n\]*\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsi2sh\[ \\t\]+\[^%\n\]*%e\[^\{\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m128h x; +volatile int n; + +void extern +avx512f_test (void) +{ + x = _mm_cvti32_sh (x, n); + x = _mm_cvt_roundi32_sh (x, n, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh-1b.c new file mode 100644 index 00000000000..d9c9a853a17 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh-1b.c @@ -0,0 +1,41 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 8 + +void NOINLINE +emulate_vcvtsi2sh(V512 *dest, V512 op1, + int value_32, __int64_t value_64, int bits) +{ + V512 v1,v2,v5,v6; + unpack_ph_2twops(op1, &v1, &v2); + if (bits == 32) + v5.xmm[0] = _mm_cvt_roundi32_ss (v1.xmm[0], value_32, _ROUND_NINT); +#ifdef __x86_64__ + else + v5.xmm[0] = _mm_cvt_roundi64_ss (v1.xmm[0], value_64, _ROUND_NINT); +#endif + v5.xmm[1] = v1.xmm[1]; + *dest = pack_twops_2ph(v5, v6); +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_vcvtsi2sh(&exp, src1, 99, 0, 32); + res.xmmh[0] = _mm_cvt_roundi32_sh(src1.xmmh[0], 99, _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_cvt_roundi32_sh"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh64-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh64-1a.c new file mode 100644 index 00000000000..5f3e5520bf1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh64-1a.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtsi2sh\[ \\t\]+\[^%\n\]*%r\[^\{\n\]*\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsi2sh\[ \\t\]+\[^%\n\]*%r\[^\{\n\]*\{ru-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m128h x; +volatile long long n; + +void extern +avx512f_test (void) +{ + x = _mm_cvti64_sh (x, n); + x = _mm_cvt_roundi64_sh (x, n, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh64-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh64-1b.c new file mode 100644 index 00000000000..6f66a87a8e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtsi2sh64-1b.c @@ -0,0 +1,41 @@ +/* { dg-do run { target { { ! ia32 } && avx512fp16 } } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 8 + +void NOINLINE +emulate_vcvtsi2sh(V512 *dest, V512 op1, + int value_32, __int64_t value_64, int bits) +{ + V512 v1,v2,v5,v6; + unpack_ph_2twops(op1, &v1, &v2); + if (bits == 32) + v5.xmm[0] = _mm_cvt_roundi32_ss (v1.xmm[0], value_32, _ROUND_NINT); +#ifdef __x86_64__ + else + v5.xmm[0] = _mm_cvt_roundi64_ss (v1.xmm[0], value_64, _ROUND_NINT); +#endif + v5.xmm[1] = v1.xmm[1]; + *dest = pack_twops_2ph(v5, v6); +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_vcvtsi2sh(&exp, src1, 0, 99, 64); + res.xmmh[0] = _mm_cvt_roundi64_sh(src1.xmmh[0], 99, _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_cvt_roundi64_sh"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh-1a.c new file mode 100644 index 00000000000..9c85da09e29 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh-1a.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtusi2sh\[ \\t\]+\[^%\n\]*%e\[^\{\n\]*\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtusi2sh\[ \\t\]+\[^%\n\]*%e\[^\{\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m128h x; +volatile unsigned n; + +void extern +avx512f_test (void) +{ + x = _mm_cvtu32_sh (x, n); + x = _mm_cvt_roundu32_sh (x, n, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh-1b.c new file mode 100644 index 00000000000..d339f0a4043 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh-1b.c @@ -0,0 +1,41 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 8 + +void NOINLINE +emulate_vcvtusi2sh(V512 *dest, V512 op1, + int value_32, __int64_t value_64, int bits) +{ + V512 v1,v2,v5,v6; + unpack_ph_2twops(op1, &v1, &v2); + if (bits == 32) + v5.xmm[0] = _mm_cvt_roundu32_ss (v1.xmm[0], value_32, _ROUND_NINT); +#ifdef __x86_64__ + else + v5.xmm[0] = _mm_cvt_roundu64_ss (v1.xmm[0], value_64, _ROUND_NINT); +#endif + v5.xmm[1] = v1.xmm[1]; + *dest = pack_twops_2ph(v5, v6); +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_vcvtusi2sh(&exp, src1, 99, 0, 32); + res.xmmh[0] = _mm_cvt_roundu32_sh(src1.xmmh[0], 99, _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_cvt_roundu32_sh"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh64-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh64-1a.c new file mode 100644 index 00000000000..1f22ac258e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh64-1a.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtusi2sh\[ \\t\]+\[^%\n\]*%r\[^\{\n\]*\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtusi2sh\[ \\t\]+\[^%\n\]*%r\[^\{\n\]*\{ru-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m128h x; +volatile unsigned long long n; + +void extern +avx512f_test (void) +{ + x = _mm_cvtu64_sh (x, n); + x = _mm_cvt_roundu64_sh (x, n, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh64-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh64-1b.c new file mode 100644 index 00000000000..20e711e1b0e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtusi2sh64-1b.c @@ -0,0 +1,41 @@ +/* { dg-do run { target { { ! ia32 } && avx512fp16 } } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 8 + +void NOINLINE +emulate_vcvtusi2sh(V512 *dest, V512 op1, + int value_32, __int64_t value_64, int bits) +{ + V512 v1,v2,v5,v6; + unpack_ph_2twops(op1, &v1, &v2); + if (bits == 32) + v5.xmm[0] = _mm_cvt_roundu32_ss (v1.xmm[0], value_32, _ROUND_NINT); +#ifdef __x86_64__ + else + v5.xmm[0] = _mm_cvt_roundu64_ss (v1.xmm[0], value_64, _ROUND_NINT); +#endif + v5.xmm[1] = v1.xmm[1]; + *dest = pack_twops_2ph(v5, v6); +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_vcvtusi2sh(&exp, src1, 0, 99, 64); + res.xmmh[0] = _mm_cvt_roundu64_sh(src1.xmmh[0], 99, _ROUND_NINT); + check_results(&res, &exp, N_ELEMS, "_mm_cvt_roundu64_sh"); + + if (n_errs != 0) { + abort (); + } +} +