doc/tm.texi.in (Condition Code): Tweak post-cc0 wording.

Ok to commit?

When eyeballing the r12-440 / bd1cd0d0e0fe / "Remove
CC0" commit, I noticed parts that could be improved.

Regarding the first change: at first I thought that just
removing the word "better" was the best choice, as the
compared part (cc0) was apparently removed, but the
paragraph after the one in the patch (still) does speak of
"implicit setting" (i.e. cc0-style), but now as hypothetical
reasoning.  So, just add that to clarify what is not-better.

The second change is just that there's no non-modern
representation, so the "Modern" qualifier is just confusing.

gcc:
	* doc/tm.texi.in (Condition Code): Tweak post-cc0 wording.
	* doc/tm.texi: Regenerate.
---
 gcc/doc/tm.texi    | 4 ++--
 gcc/doc/tm.texi.in | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

On Sat, May 15, 2021 at 08:44:29PM +0200, Hans-Peter Nilsson via Gcc-patches wrote:
> When eyeballing the r12-440 / bd1cd0d0e0fe / "Remove
> CC0" commit, I noticed parts that could be improved.
> 
> Regarding the first change: at first I thought that just
> removing the word "better" was the best choice, as the
> compared part (cc0) was apparently removed, but the
> paragraph after the one in the patch (still) does speak of
> "implicit setting" (i.e. cc0-style), but now as hypothetical
> reasoning.  So, just add that to clarify what is not-better.

It is better to remove that hypothetical, imho.

> Condition codes in GCC are represented as registers,

s/,/./ and remove the rest of this paragraph?

> -which provides better schedulability for
> +which provides better schedulability than implicit clobbering for
>  architectures that do have a condition code register, but on which
>  most instructions do not affect it.  The latter category includes
>  most RISC machines.


>  Condition codes in GCC are represented as registers,

s/,/./ and remove the rest as well?

> -which provides better schedulability for
> +which provides better schedulability than implicit clobbering for
>  architectures that do have a condition code register, but on which
>  most instructions do not affect it.  The latter category includes
>  most RISC machines.


> The second change is just that there's no non-modern
> representation, so the "Modern" qualifier is just confusing.

That is just fine of course :-)


I would commit such changes as obvious btw, so if you do so as well, you
can blame me if anyone asks!


Segher

> From: Segher Boessenkool <segher@kernel.crashing.org>
> Date: Sun, 16 May 2021 18:18:17 +0200

> On Sat, May 15, 2021 at 08:44:29PM +0200, Hans-Peter Nilsson via Gcc-patches wrote:
> > When eyeballing the r12-440 / bd1cd0d0e0fe / "Remove
> > CC0" commit, I noticed parts that could be improved.
> > 
> > Regarding the first change: at first I thought that just
> > removing the word "better" was the best choice, as the
> > compared part (cc0) was apparently removed, but the
> > paragraph after the one in the patch (still) does speak of
> > "implicit setting" (i.e. cc0-style), but now as hypothetical
> > reasoning.  So, just add that to clarify what is not-better.
> 
> It is better to remove that hypothetical, imho.
> 
> > Condition codes in GCC are represented as registers,
> 
> s/,/./ and remove the rest of this paragraph?

Perhaps.  Let's see what a doc maintainer says.

> I would commit such changes as obvious btw, so if you do so as well, you
> can blame me if anyone asks!

The second one likely, but for the first one there was
"obviously" a few different suggestions.

Thanks, for the review!

brgds, H-P