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Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT009.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR08MB3785 X-Spam-Status: No, score=-14.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, MSGID_FROM_MTA_HEADER, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Alex Coplan via Gcc-patches From: Alex Coplan Reply-To: Alex Coplan Cc: Richard Earnshaw , Richard Sandiford Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Hi all, This patch fixes PR99988 which shows us generating large (> 250) sequences of back-to-back bti j instructions. The fix is simply to avoid inserting bti j instructions at the target of a jump table if we've already inserted one for a given label. Testing: * Bootstrapped and regtested on aarch64-linux-gnu (with and without -mbranch-protection=standard), no regressions. Presumably this is stage 1 material since the bug isn't a regression? If so, OK for GCC 12 stage 1? Thanks, Alex gcc/ChangeLog: PR target/99988 * config/aarch64/aarch64-bti-insert.c (aarch64_bti_j_insn_p): New. (rest_of_insert_bti): Avoid inserting duplicate bti j insns for jump table targets. gcc/testsuite/ChangeLog: PR target/99988 * gcc.target/aarch64/pr99988.c: New test. diff --git a/gcc/config/aarch64/aarch64-bti-insert.c b/gcc/config/aarch64/aarch64-bti-insert.c index 936649769c7..943fa3c1097 100644 --- a/gcc/config/aarch64/aarch64-bti-insert.c +++ b/gcc/config/aarch64/aarch64-bti-insert.c @@ -120,6 +120,13 @@ aarch64_pac_insn_p (rtx x) return false; } +static bool +aarch64_bti_j_insn_p (rtx_insn *insn) +{ + rtx pat = PATTERN (insn); + return GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_BTI_J; +} + /* Insert the BTI instruction. */ /* This is implemented as a late RTL pass that runs before branch shortening and does the following. */ @@ -165,6 +172,9 @@ rest_of_insert_bti (void) for (j = GET_NUM_ELEM (vec) - 1; j >= 0; --j) { label = as_a (XEXP (RTVEC_ELT (vec, j), 0)); + if (aarch64_bti_j_insn_p (next_nonnote_insn (label))) + continue; + bti_insn = gen_bti_j (); emit_insn_after (bti_insn, label); } diff --git a/gcc/testsuite/gcc.target/aarch64/pr99988.c b/gcc/testsuite/gcc.target/aarch64/pr99988.c new file mode 100644 index 00000000000..2d87f41a717 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr99988.c @@ -0,0 +1,66 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbranch-protection=standard" } */ +/* { dg-final { scan-assembler-times {bti j} 13 } } */ +int a; +int c(); +int d(); +int e(); +int f(); +int g(); +void h() { + switch (a) { + case 0: + case 56: + case 57: + break; + case 58: + case 59: + case 61: + case 62: + c(); + case 64: + case 63: + d(); + case 66: + case 65: + d(); + case 68: + case 67: + d(); + case 69: + case 70: + d(); + case 71: + case 72: + case 88: + case 87: + d(); + case 90: + case 89: + d(); + case 92: + case 1: + d(); + case 93: + case 73: + case 4: + e(); + case 76: + case 5: + f(); + case 7: + case 8: + case 84: + case 85: + break; + case 6: + case 299: + case 9: + case 80: + case 2: + case 3: + e(); + default: + g(); + } +}