From patchwork Mon Jan 25 09:02:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu X-Patchwork-Id: 1431119 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=GXEKQe0k; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DPP5Q2RMjz9rx8 for ; Mon, 25 Jan 2021 20:02:32 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A1DAD38930D9; Mon, 25 Jan 2021 09:02:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A1DAD38930D9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1611565347; bh=FvrZ1ozmef1KAhCUYX41IAuUy2LSeRibCexEjMC7dHY=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=GXEKQe0kewzxJq4Oi46Q5RoNJTON/FbF+IoB9c1IR3eq+FjS/Jsw6MruI6BQbw0a2 F/7cDJip3P3ld6ESdDC0eNYBPPM8xghLFmVHFMMENJQUelEjbHB4a5L/ICe2rO62+Q rqAJKU9d3Z1fEcgRpKdV8QVk6l321pHSRksUbfZo= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by sourceware.org (Postfix) with ESMTPS id C612C3858C27 for ; Mon, 25 Jan 2021 09:02:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org C612C3858C27 Received: by mail-wr1-x434.google.com with SMTP id 6so11404295wri.3 for ; Mon, 25 Jan 2021 01:02:24 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=FvrZ1ozmef1KAhCUYX41IAuUy2LSeRibCexEjMC7dHY=; b=I04IB+E/hDCsqqbZF6Vz68UM+Tk8lvGqtlNaRnbbAISXvm5XcbCEOnZr0ArXA7R3ho zNyFsP1Au3kA4CNJSIDkioTBG6T73HorBs2EHg3ns8xlSH8vKjp4mkyFKbT45BO7gQMH V9E7vXqUBE3fKgVPeRPJKAtuNms9V3llAia39JsBlBid/dr3+KEw++f9NY+J5Q+xIDjJ AfOJZBCHYJ9e4d9DqX6H0oFxPOjnEnAz7l6y4kqvZLBz722n11v4Jc4xwr3XYpBy5g35 zMa/EjlQQuA3acTbIjqQty83umya32klFICnV2v4wzAJmbJNKgEOyQ5aECjQ6Sg6gZBA ebGg== X-Gm-Message-State: AOAM532q9rbkBJr4YlHiVbfk6z5mqz0rptGjGSqNZ++2I7zZTLPIVJfb 2NA7guHzHEUp0LGtmLEcaPwRoLPsmI7oQQ== X-Google-Smtp-Source: ABdhPJyPR0Y5yODa5GoKFnktPsvUDMbTNDOkZnb4a+2vCpefSh8nENWU+SMd8J09D+czcKa+qiR21Q== X-Received: by 2002:a5d:538b:: with SMTP id d11mr741031wrv.334.1611565343480; Mon, 25 Jan 2021 01:02:23 -0800 (PST) Received: from localhost.localdomain ([86.105.9.116]) by smtp.gmail.com with ESMTPSA id 62sm21062399wmd.34.2021.01.25.01.02.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Jan 2021 01:02:23 -0800 (PST) X-Google-Original-From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Subject: [backport gcc10] arc: Use separate predicated patterns for mpyd(u) Date: Mon, 25 Jan 2021 11:02:16 +0200 Message-Id: <20210125090216.414840-1-claziss@synopsys.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Claudiu Zissulescu via Gcc-patches From: Claudiu Zissulescu Reply-To: Claudiu Zissulescu Cc: fbedard@synopsys.com, vgupta@synopsys.com Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" From: Claudiu Zissulescu The compiler can match mpyd.eq r0,r1,r0 as a predicated instruction, which is incorrect. The mpyd(u) instruction takes as input two 32-bit registers, returning into a double 64-bit even-odd register pair. For the predicated case, the ARC instruction decoder expects the destination register to be the same as the first input register. In the big-endian case the result is swaped in the destination register pair, however, the instruction encoding remains the same. Refurbish the mpyd(u) patterns to take into account the above observation. gcc/ 2020-12-11 Claudiu Zissulescu * config/arc/arc.md (mpyd_arcv2hs): New template pattern. (*pmpyd_arcv2hs): Likewise. (*pmpyd_imm_arcv2hs): Likewise. (mpyd_arcv2hs): Moved into above template. (mpyd_imm_arcv2hs): Moved into above template. (mpydu_arcv2hs): Likewise. (mpydu_imm_arcv2hs): Likewise. (su_optab): New optab prefix for sign/zero-extending operations. gcc/testsuite/ 2020-12-11 Claudiu Zissulescu * gcc.target/arc/pmpyd.c: New test. * gcc.target/arc/tmac-1.c: Update. Signed-off-by: Claudiu Zissulescu (cherry picked from commit f7ad4446274831234e5acd3506fd2e01c7594c6a) --- gcc/config/arc/arc.md | 101 +++++++++++++------------- gcc/testsuite/gcc.target/arc/pmpyd.c | 15 ++++ gcc/testsuite/gcc.target/arc/tmac-1.c | 2 +- 3 files changed, 67 insertions(+), 51 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arc/pmpyd.c diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 398034d361e..a79db6da89e 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -871,6 +871,8 @@ (define_mode_attr SQH_postfix [(QI "b") (HI "%_")]) (define_code_iterator SEZ [sign_extend zero_extend]) (define_code_attr SEZ_prefix [(sign_extend "sex") (zero_extend "ext")]) +; Optab prefix for sign/zero-extending operations +(define_code_attr su_optab [(sign_extend "") (zero_extend "u")]) (define_insn "*xt_cmp0_noout" [(set (match_operand 0 "cc_set_register" "") @@ -6289,66 +6291,65 @@ (define_insn "macu_r" (set_attr "predicable" "no") (set_attr "cond" "nocond")]) -(define_insn "mpyd_arcv2hs" - [(set (match_operand:DI 0 "even_register_operand" "=Rcr, r") - (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " 0, c")) - (sign_extend:DI (match_operand:SI 2 "register_operand" " c, c")))) +(define_insn "mpyd_arcv2hs" + [(set (match_operand:DI 0 "even_register_operand" "=r") + (mult:DI (SEZ:DI (match_operand:SI 1 "register_operand" "r")) + (SEZ:DI (match_operand:SI 2 "register_operand" "r")))) (set (reg:DI ARCV2_ACC) (mult:DI - (sign_extend:DI (match_dup 1)) - (sign_extend:DI (match_dup 2))))] + (SEZ:DI (match_dup 1)) + (SEZ:DI (match_dup 2))))] "TARGET_PLUS_MACD" - "mpyd%? %0,%1,%2" - [(set_attr "length" "4,4") - (set_attr "iscompact" "false") - (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) - -(define_insn "mpyd_imm_arcv2hs" - [(set (match_operand:DI 0 "even_register_operand" "=Rcr, r,r,Rcr, r") - (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " 0, c,0, 0, c")) - (match_operand 2 "immediate_operand" " L, L,I,Cal,Cal"))) + "mpyd%?\\t%0,%1,%2" + [(set_attr "length" "4") + (set_attr "iscompact" "false") + (set_attr "type" "multi") + (set_attr "predicable" "no")]) + +(define_insn "*pmpyd_arcv2hs" + [(set (match_operand:DI 0 "even_register_operand" "=r") + (mult:DI + (SEZ:DI (match_operand:SI 1 "even_register_operand" "%0")) + (SEZ:DI (match_operand:SI 2 "register_operand" "r")))) (set (reg:DI ARCV2_ACC) - (mult:DI (sign_extend:DI (match_dup 1)) - (match_dup 2)))] + (mult:DI + (SEZ:DI (match_dup 1)) + (SEZ:DI (match_dup 2))))] "TARGET_PLUS_MACD" - "mpyd%? %0,%1,%2" - [(set_attr "length" "4,4,4,8,8") - (set_attr "iscompact" "false") - (set_attr "type" "multi") - (set_attr "predicable" "yes,no,no,yes,no") - (set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond")]) - -(define_insn "mpydu_arcv2hs" - [(set (match_operand:DI 0 "even_register_operand" "=Rcr, r") - (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" " 0, c")) - (zero_extend:DI (match_operand:SI 2 "register_operand" " c, c")))) + "mpyd%?\\t%0,%1,%2" + [(set_attr "length" "4") + (set_attr "iscompact" "false") + (set_attr "type" "multi") + (set_attr "predicable" "yes")]) + +(define_insn "mpyd_imm_arcv2hs" + [(set (match_operand:DI 0 "even_register_operand" "=r,r, r") + (mult:DI (SEZ:DI (match_operand:SI 1 "register_operand" "r,0, r")) + (match_operand 2 "immediate_operand" "L,I,Cal"))) (set (reg:DI ARCV2_ACC) - (mult:DI (zero_extend:DI (match_dup 1)) - (zero_extend:DI (match_dup 2))))] + (mult:DI (SEZ:DI (match_dup 1)) + (match_dup 2)))] "TARGET_PLUS_MACD" - "mpydu%? %0,%1,%2" - [(set_attr "length" "4,4") - (set_attr "iscompact" "false") - (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) - -(define_insn "mpydu_imm_arcv2hs" - [(set (match_operand:DI 0 "even_register_operand" "=Rcr, r,r,Rcr, r") - (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" " 0, c,0, 0, c")) - (match_operand 2 "immediate_operand" " L, L,I,Cal,Cal"))) + "mpyd%?\\t%0,%1,%2" + [(set_attr "length" "4,4,8") + (set_attr "iscompact" "false") + (set_attr "type" "multi") + (set_attr "predicable" "no")]) + +(define_insn "*pmpyd_imm_arcv2hs" + [(set (match_operand:DI 0 "even_register_operand" "=r,r") + (mult:DI + (SEZ:DI (match_operand:SI 1 "even_register_operand" "0,0")) + (match_operand 2 "immediate_operand" "L,Cal"))) (set (reg:DI ARCV2_ACC) - (mult:DI (zero_extend:DI (match_dup 1)) + (mult:DI (SEZ:DI (match_dup 1)) (match_dup 2)))] "TARGET_PLUS_MACD" - "mpydu%? %0,%1,%2" - [(set_attr "length" "4,4,4,8,8") - (set_attr "iscompact" "false") - (set_attr "type" "multi") - (set_attr "predicable" "yes,no,no,yes,no") - (set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond")]) + "mpyd%?\\t%0,%1,%2" + [(set_attr "length" "4,8") + (set_attr "iscompact" "false") + (set_attr "type" "multi") + (set_attr "predicable" "yes")]) (define_insn "*add_shift" [(set (match_operand:SI 0 "register_operand" "=q,r,r") diff --git a/gcc/testsuite/gcc.target/arc/pmpyd.c b/gcc/testsuite/gcc.target/arc/pmpyd.c new file mode 100644 index 00000000000..0eb0ff7f11b --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/pmpyd.c @@ -0,0 +1,15 @@ +/* { dg-do assemble } */ +/* { dg-skip-if "" { ! { clmcpu } } } */ +/* { dg-options "-mcpu=hs38 -Os -EB" } */ + +/* This example is found during big-endian build. The compiler is + matching mpydu.hi r12,r13,r3 as a predicated instruction, which is + incorrect. The error is due to different predicates between the + output operand and the first operand of the instruction. */ +unsigned int test(unsigned int x, unsigned long long y) +{ + y /= 0x20000000; + if (x > 1) + y *= x; + return y; +} diff --git a/gcc/testsuite/gcc.target/arc/tmac-1.c b/gcc/testsuite/gcc.target/arc/tmac-1.c index 3fcabf5fff2..5b302cad4a4 100644 --- a/gcc/testsuite/gcc.target/arc/tmac-1.c +++ b/gcc/testsuite/gcc.target/arc/tmac-1.c @@ -7,5 +7,5 @@ /* { dg-final { scan-assembler "macd " } } */ /* { dg-final { scan-assembler "macdu" } } */ -/* { dg-final { scan-assembler "mpyd " } } */ +/* { dg-final { scan-assembler "mpyd\\t" } } */ /* { dg-final { scan-assembler "mpydu" } } */