diff mbox series

[v2,16/16] Testsuite: Add initial tests for NEON (incomplete)

Message ID 20200925143145.GA31591@arm.com
State New
Headers show
Series middle-end Add support for SLP vectorization of complex number instructions. | expand

Commit Message

Tamar Christina Sept. 25, 2020, 2:31 p.m. UTC 
Hi All,

These are just initial testcases to show what the patch is testing for,
however it is incomplete and I am working on better test setup
to test all targets and add middle-end tests.

These were just included for completeness.

Thanks,
Tamar

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays-autovec-270.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays-autovec-90.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_1.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_2.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_3.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_4.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_5.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_6.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcadd-complex-autovec.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_1.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_2.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_3.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_4.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_5.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_6.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex-autovec.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_1.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_1.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_2.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_3.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_2.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_1.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_2.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_3.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_3.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_1.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_2.c: New test.
	* gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_3.c: New test.

--
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays-autovec-270.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays-autovec-270.c
new file mode 100644
index 0000000000000000000000000000000000000000..8f660f392153c3a6a83b31486e275be316c6ad2b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays-autovec-270.c
@@ -0,0 +1,13 @@ 
+/* { dg-skip-if "" { *-*-* } } */
+
+#define N 200
+
+__attribute__ ((noinline))
+void calc (TYPE a[N], TYPE b[N], TYPE *c)
+{
+  for (int i=0; i < N; i+=2)
+    {
+      c[i] = a[i] + b[i+1];
+      c[i+1] = a[i+1] - b[i];
+    }
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays-autovec-90.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays-autovec-90.c
new file mode 100644
index 0000000000000000000000000000000000000000..14014b9d4f2c41e75be3e253d2e47e639e4224c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays-autovec-90.c
@@ -0,0 +1,12 @@ 
+/* { dg-skip-if "" { *-*-* } } */
+#define N 200
+
+__attribute__ ((noinline))
+void calc (TYPE a[N], TYPE b[N], TYPE *c)
+{
+  for (int i=0; i < N; i+=2)
+    {
+      c[i] = a[i] - b[i+1];
+      c[i+1] = a[i+1] + b[i];
+    }
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..997d9065504a9a16d3ea1316f7ea4208b3516c55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_1.c
@@ -0,0 +1,30 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_df } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE double
+#include "vcadd-arrays-autovec-90.c"
+
+extern void abort(void);
+
+int main()
+{
+  TYPE a[N] = {1.0, 2.0, 3.0, 4.0};
+  TYPE b[N] = {4.0, 2.0, 1.5, 4.5};
+  TYPE c[N] = {0};
+  calc (a, b, c);
+
+  if (c[0] != -1.0 || c[1] != 6.0)
+    abort ();
+
+  if (c[2] != -1.5 || c[3] != 5.5)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.2d, v[0-9]+\.2d, v[0-9]+\.2d, #90} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-not {vcadd\.} { target { arm*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..8ab2aa75e261e0d885fb8042c09b6e42284dea85
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_2.c
@@ -0,0 +1,30 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_sf } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE float
+#include "vcadd-arrays-autovec-90.c"
+
+extern void abort(void);
+
+int main()
+{
+  TYPE a[N] = {1.0, 2.0, 3.0, 4.0};
+  TYPE b[N] = {4.0, 2.0, 1.5, 4.5};
+  TYPE c[N] = {0};
+  calc (a, b, c);
+
+  if (c[0] != -1.0 || c[1] != 6.0)
+    abort ();
+
+  if (c[2] != -1.5 || c[3] != 5.5)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.4s, v[0-9]+\.4s, v[0-9]+\.4s, #90} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {vcadd\.f32\tq[0-9]+, q[0-9]+, q[0-9]+, #(?:0|90)} 2 { target { arm*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..8002d4efa003bb8af6a6592334e7749da336875e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_3.c
@@ -0,0 +1,31 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_hf } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast  -march=armv8.3-a+fp16 -save-temps" } */
+
+#define TYPE _Float16
+#include "vcadd-arrays-autovec-90.c"
+
+extern void abort(void);
+
+int main()
+{
+  TYPE a[N] = {1.0, 2.0, 3.0, 4.0};
+  TYPE b[N] = {4.0, 2.0, 1.5, 4.5};
+  TYPE c[N] = {0};
+  calc (a, b, c);
+
+  if (c[0] != -1.0 || c[1] != 6.0)
+    abort ();
+
+  if (c[2] != -1.5 || c[3] != 5.5)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.8h, v[0-9]+\.8h, v[0-9]+\.8h, #90} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {vcadd\.f16\tq[0-9]+, q[0-9]+, q[0-9]+, #90} 1 { target { arm*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_4.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_4.c
new file mode 100644
index 0000000000000000000000000000000000000000..601d6886a4c999d010ca2e8a5babad066d5fa0a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_4.c
@@ -0,0 +1,30 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_df } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE double
+#include "vcadd-arrays-autovec-270.c"
+
+extern void abort(void);
+
+int main()
+{
+  TYPE a[N] = {1.0, 2.0, 3.0, 4.0};
+  TYPE b[N] = {4.0, 2.0, 1.5, 4.5};
+  TYPE c[N] = {0};
+  calc (a, b, c);
+
+  if (c[0] != 3.0 || c[1] != -2.0)
+    abort ();
+
+  if (c[2] != 7.5 || c[3] != 2.5)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.2d, v[0-9]+\.2d, v[0-9]+\.2d, #270} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-not {vcadd\.} { target { arm*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_5.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_5.c
new file mode 100644
index 0000000000000000000000000000000000000000..f7851bc7304bf671f3e14bb08e7dc434e867a29c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_5.c
@@ -0,0 +1,30 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_sf } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE float
+#include "vcadd-arrays-autovec-270.c"
+
+extern void abort(void);
+
+int main()
+{
+  TYPE a[N] = {1.0, 2.0, 3.0, 4.0};
+  TYPE b[N] = {4.0, 2.0, 1.5, 4.5};
+  TYPE c[N] = {0};
+  calc (a, b, c);
+
+  if (c[0] != 3.0 || c[1] != -2.0)
+    abort ();
+
+  if (c[2] != 7.5 || c[3] != 2.5)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.4s, v[0-9]+\.4s, v[0-9]+\.4s, #270} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {vcadd\.f32\tq[0-9]+, q[0-9]+, q[0-9]+, #270} 1 { target { arm*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_6.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_6.c
new file mode 100644
index 0000000000000000000000000000000000000000..02172be3647852cd3a959a6b1aef82e3a4c5f28d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-arrays_6.c
@@ -0,0 +1,31 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_hf } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast  -march=armv8.3-a+fp16 -save-temps" } */
+
+#define TYPE _Float16
+#include "vcadd-arrays-autovec-270.c"
+
+extern void abort(void);
+
+int main()
+{
+  TYPE a[N] = {1.0, 2.0, 3.0, 4.0};
+  TYPE b[N] = {4.0, 2.0, 1.5, 4.5};
+  TYPE c[N] = {0};
+  calc (a, b, c);
+
+  if (c[0] != 3.0 || c[1] != -2.0)
+    abort ();
+
+  if (c[2] != 7.5 || c[3] != 2.5)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.8h, v[0-9]+\.8h, v[0-9]+\.8h, #270} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {vcadd\.f16\tq[0-9]+, q[0-9]+, q[0-9]+, #270} 1 { target { arm*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex-autovec.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex-autovec.c
new file mode 100644
index 0000000000000000000000000000000000000000..2a301e6ec0a9ba23a16c39d9c36ee281422f1803
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex-autovec.c
@@ -0,0 +1,12 @@ 
+/* { dg-skip-if "" { *-*-* } } */
+
+#include <complex.h>
+
+#define N 200
+
+__attribute__ ((noinline))
+void calc (TYPE complex a[N], TYPE complex b[N], TYPE complex c[N])
+{
+  for (int i=0; i < N; i++)
+    c[i] = a[i] + b[i] ROT;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..aebe0b8bdeee25d7ae6e387b006de9413ecbc13e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_1.c
@@ -0,0 +1,33 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_df } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE double
+#define ROT * I
+#include "vcadd-complex-autovec.c"
+
+extern void abort(void);
+
+#include <stdio.h>
+
+int main()
+{
+  TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+  TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+  TYPE complex c[N] = {0};
+  calc (a, b, c);
+
+  if (creal (c[0]) != -1.0 || cimag (c[0]) != 6.0)
+    abort ();
+
+  if (creal (c[1]) != -1.5 || cimag (c[1]) != 5.5)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.2d, v[0-9]+\.2d, v[0-9]+\.2d, #90} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-not {vcadd\.} { target { arm*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..891e9874d2d66b9849809c3f7ca3c31044256f99
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_2.c
@@ -0,0 +1,31 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_sf } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE float
+#define ROT * I
+#include "vcadd-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+  TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+  TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+  TYPE complex c[N] = {0};
+  calc (a, b, c);
+
+  if (creal (c[0]) != -1.0 || cimag (c[0]) != 6.0)
+    abort ();
+
+  if (creal (c[1]) != -1.5 || cimag (c[1]) != 5.5)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.4s, v[0-9]+\.4s, v[0-9]+\.4s, #90} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {vcadd\.f32\tq[0-9]+, q[0-9]+, q[0-9]+, #90} 1 { target { arm*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..871d64a9bab0b08433f55eedd890146058526a1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_3.c
@@ -0,0 +1,32 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_hf } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast  -march=armv8.3-a+fp16 -save-temps" } */
+
+#define TYPE _Float16
+#define ROT * I
+#include "vcadd-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+  TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+  TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+  TYPE complex c[N] = {0};
+  calc (a, b, c);
+
+  if (creal (c[0]) != -1.0 || cimag (c[0]) != 6.0)
+    abort ();
+
+  if (creal (c[1]) != -1.5 || cimag (c[1]) != 5.5)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.8h, v[0-9]+\.8h, v[0-9]+\.8h, #90} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {vcadd\.f32\tq[0-9]+, q[0-9]+, q[0-9]+, #90} 1 { target { arm*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_4.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_4.c
new file mode 100644
index 0000000000000000000000000000000000000000..7c9278945fc28e1350ef8ac9a4ddfdac56da14c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_4.c
@@ -0,0 +1,31 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_df } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE double
+#define ROT * I * I * I
+#include "vcadd-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+  TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+  TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+  TYPE complex c[N] = {0};
+  calc (a, b, c);
+
+  if (creal (c[0]) != 3.0 || cimag (c[0]) != -2.0)
+    abort ();
+
+  if (creal (c[1]) != 7.5 || cimag (c[1]) != 2.5)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.2d, v[0-9]+\.2d, v[0-9]+\.2d, #270} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-not {fcadd\.} { target { arm*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_5.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_5.c
new file mode 100644
index 0000000000000000000000000000000000000000..a431fc82155c5eccf02cf4b66313caf989777084
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_5.c
@@ -0,0 +1,31 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_sf } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE float
+#define ROT * I * I * I
+#include "vcadd-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+  TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+  TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+  TYPE complex c[N] = {0};
+  calc (a, b, c);
+
+ if (creal (c[0]) != 3.0 || cimag (c[0]) != -2.0)
+    abort ();
+
+  if (creal (c[1]) != 7.5 || cimag (c[1]) != 2.5)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.4s, v[0-9]+\.4s, v[0-9]+\.4s, #270} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {vcadd\.f32\tq[0-9]+, q[0-9]+, q[0-9]+, #270} 1 { target { arm*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_6.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_6.c
new file mode 100644
index 0000000000000000000000000000000000000000..6e1b04d4088b9dd503f33aa6e85196a61db0ee5c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcadd-complex_6.c
@@ -0,0 +1,32 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_hf } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast  -march=armv8.3-a+fp16 -save-temps" } */
+
+#define TYPE _Float16
+#define ROT * I * I * I
+#include "vcadd-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+  TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+  TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+  TYPE complex c[N] = {0};
+  calc (a, b, c);
+
+ if (creal (c[0]) != 3.0 || cimag (c[0]) != -2.0)
+    abort ();
+
+  if (creal (c[1]) != 7.5 || cimag (c[1]) != 2.5)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcadd\tv[0-9]+\.8h, v[0-9]+\.8h, v[0-9]+\.8h, #270} 1 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {vcadd\.f16\tq[0-9]+, q[0-9]+, q[0-9]+, #270} 1 { target { arm*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex-autovec.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex-autovec.c
new file mode 100644
index 0000000000000000000000000000000000000000..1ad7cc319eeef2ea15f530997a9ffc09571ea02e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex-autovec.c
@@ -0,0 +1,11 @@ 
+/* { dg-skip-if "" { *-*-* } } */
+#include <complex.h>
+
+#define N 200
+
+__attribute__ ((noinline, noipa))
+void calc (TYPE complex a[N], TYPE complex b[N], TYPE complex c[N])
+{
+  for (int i=0; i < N; i++)
+    c[i] += a[i] * b[i] ROT;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..6b5baf013ce285cfa0a28cb9128d839d6ad3d4eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_1.c
@@ -0,0 +1,33 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_df } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+/* { dg-keep-saved-temps ".s" ".o" ".exe" } */
+#define TYPE double
+#define ROT 
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+#include <stdio.h>
+
+int main()
+{
+  TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+  TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+  TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+  calc (a, b, c);
+
+  if (creal (c[0]) != 2.5 || cimag (c[0]) != 11.5)
+    abort ();
+
+  if (creal (c[1]) != -11.5 || cimag (c[1]) != 21.0)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+\.2d, v[0-9]+\.2d, v[0-9]+\.2d, #(?:0|90)} 2 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-not {vcmla\.} { target { arm*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..2d6fc3354ad5b32c4d636efbeeefdc756d7d2b7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_1.c
@@ -0,0 +1,31 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_df } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE double
+#define ROT * I * I
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+  TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+  TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+  TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+  calc (a, b, c);
+
+  if (creal (c[0]) != 2.5 || cimag (c[0]) != -8.5)
+    abort ();
+
+  if (creal (c[1]) != 15.5 || cimag (c[1]) != -18.0)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+\.2d, v[0-9]+\.2d, v[0-9]+\.2d, #(?:180|270)} 2 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-not {vcmla\.} { target { arm*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..f4ce831705b09288ef2ca52c26a26fef1d8cca20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_2.c
@@ -0,0 +1,31 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_sf } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE float
+#define ROT * I * I
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+  TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+  TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+  TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+  calc (a, b, c);
+
+  if (creal (c[0]) != 2.5 || cimag (c[0]) != -8.5)
+    abort ();
+
+  if (creal (c[1]) != 15.5 || cimag (c[1]) != -18.0)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+\.4s, v[0-9]+\.4s, v[0-9]+\.4s, #(?:180|270)} 2 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {vcmla\.f32\tq[0-9]+, q[0-9]+, q[0-9]+, #(?:180|270)} 2 { target { arm*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..7a6aed992322753dc928f1db9689f58f02702745
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_180_3.c
@@ -0,0 +1,32 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_hf } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast  -march=armv8.3-a+fp16 -save-temps" } */
+
+#define TYPE _Float16
+#define ROT * I * I
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+  TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+  TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+  TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+  calc (a, b, c);
+
+  if (creal (c[0]) != 2.5 || cimag (c[0]) != -8.5)
+    abort ();
+
+  if (creal (c[1]) != 15.5 || cimag (c[1]) != -18.0)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+\.8h, v[0-9]+\.8h, v[0-9]+\.8h, #(?:180|270)} 2 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {vcmla\.f16\tq[0-9]+, q[0-9]+, q[0-9]+, #(?:180|270)} 2 { target { arm*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..70198d0eb52cf1be2c3df4c99ae5868d7abafd38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_2.c
@@ -0,0 +1,31 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_sf } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE float
+#define ROT
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+  TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+  TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+  TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+  calc (a, b, c);
+
+  if (creal (c[0]) != 2.5 || cimag (c[0]) != 11.5)
+    abort ();
+
+  if (creal (c[1]) != -11.5 || cimag (c[1]) != 21.0)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+\.4s, v[0-9]+\.4s, v[0-9]+\.4s, #(?:0|90)} 2 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {vcmla\.f32\tq[0-9]+, q[0-9]+, q[0-9]+, #(?:0|90)} 2 { target { arm*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..ccc4a8723b28f81de0ee93abeff6d8a09e841260
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_1.c
@@ -0,0 +1,30 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_df } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE double
+#define ROT * I * I * I
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+  TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+  TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+  TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+  calc (a, b, c);
+
+  if (creal (c[0]) != 12.5 || cimag (c[0]) != 1.5)
+    abort ();
+
+  if (creal (c[1]) != 21.5 || cimag (c[1]) != 15.0)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not {fcmla} { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-not {vcmla\.} { target { arm*-*-* } } } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..b9748e3674f3594369d81f8587f5d5a424c13562
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_2.c
@@ -0,0 +1,30 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_sf } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE float
+#define ROT * I * I * I
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+  TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+  TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+  TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+  calc (a, b, c);
+
+  if (creal (c[0]) != 12.5 || cimag (c[0]) != 1.5)
+    abort ();
+
+  if (creal (c[1]) != 21.5 || cimag (c[1]) != 15.0)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not {fcmla} { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-not {vcmla\.} { target { arm*-*-* } } } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..09e489ffcd302b4bdba2148c3a11529344df2a11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_270_3.c
@@ -0,0 +1,31 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_hf } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast  -march=armv8.3-a+fp16 -save-temps" } */
+
+#define TYPE _Float16
+#define ROT * I * I * I
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+  TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+  TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+  TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+  calc (a, b, c);
+
+  if (creal (c[0]) != 12.5 || cimag (c[0]) != 1.5)
+    abort ();
+
+  if (creal (c[1]) != 21.5 || cimag (c[1]) != 15.0)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not {fcmla} { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-not {vcmla\.} { target { arm*-*-* } } } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..2259587237b510149a8369761f6b3b92d1d79cb2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_3.c
@@ -0,0 +1,32 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_hf } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast  -march=armv8.3-a+fp16 -save-temps" } */
+
+#define TYPE _Float16
+#define ROT
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+  TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+  TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+  TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+  calc (a, b, c);
+
+  if (creal (c[0]) != 2.5 || cimag (c[0]) != 11.5)
+    abort ();
+
+  if (creal (c[1]) != -11.5 || cimag (c[1]) != 21.0)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times {fcmla\tv[0-9]+\.8h, v[0-9]+\.8h, v[0-9]+\.8h, #(?:0|90)} 2 { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-times {vcmla\.f16\tq[0-9]+, q[0-9]+, q[0-9]+, #(?:0|90)} 2 { target { arm*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..acc3fad76791d7038c3f96d5333b68ce9af99468
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_1.c
@@ -0,0 +1,33 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_df } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE double
+#define ROT * I
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+#include <stdio.h>
+
+int main()
+{
+  TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+  TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+  TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+  calc (a, b, c);
+
+  if (creal (c[0]) != -7.5 || cimag (c[0]) != 1.5)
+    abort ();
+
+  if (creal (c[1]) != -17.5 || cimag (c[1]) != -12.0)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not {fcmla} { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-not {vcmla\.} { target { arm*-*-* } } } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..d913a192bce0b9d059297c4c2024814a59dabd0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_2.c
@@ -0,0 +1,30 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_sf } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast -save-temps" } */
+
+#define TYPE float
+#define ROT * I
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+  TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+  TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+  TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+  calc (a, b, c);
+
+  if (creal (c[0]) != -7.5 || cimag (c[0]) != 1.5)
+    abort ();
+
+  if (creal (c[1]) != -17.5 || cimag (c[1]) != -12.0)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not {fcmla} { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-not {vcmla\.} { target { arm*-*-* } } } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..08a77a8f8215db944d8d0438b310ce32f68a57ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcmla-complex_90_3.c
@@ -0,0 +1,31 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_3a_complex_neon_ok } */
+/* { dg-require-effective-target vect_complex_rot_hf } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
+/* { dg-add-options arm_v8_3a_complex_neon } */
+/* { dg-additional-options "-Ofast  -march=armv8.3-a+fp16 -save-temps" } */
+
+#define TYPE _Float16
+#define ROT * I
+#include "vcmla-complex-autovec.c"
+
+extern void abort(void);
+
+int main()
+{
+  TYPE complex a[N] = {1.0 + 2.0 * I, 3.0 + 4.0 * I};
+  TYPE complex b[N] = {4.0 + 2.0 * I, 1.5 + 4.5 * I};
+  TYPE complex c[N] = {2.5 + 1.5 * I, 2.0 + 1.5 * I};
+  calc (a, b, c);
+
+  if (creal (c[0]) != -7.5 || cimag (c[0]) != 1.5)
+    abort ();
+
+  if (creal (c[1]) != -17.5 || cimag (c[1]) != -12.0)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not {fcmla} { target { aarch64*-*-* } } } } */
+/* { dg-final { scan-assembler-not {vcmla\.} { target { arm*-*-* } } } } */