diff mbox series

[2/2] rs6000: Add tests for _mm_insert_epi{8,32,64}

Message ID 20200923221245.243397-2-pc@us.ibm.com
State New
Headers show
Series [1/2] rs6000: Support _mm_insert_epi{8,32,64} | expand

Commit Message

Paul A. Clarke Sept. 23, 2020, 10:12 p.m. UTC 
Copied from gcc.target/i386.

2020-09-23  Paul A. Clarke  <pc@us.ibm.com>

gcc/testsuite/ChangeLog:

	* gcc.target/powerpc/sse4_1-pinsrb.c: New test.
	* gcc.target/powerpc/sse4_1-pinsrd.c: New test.
	* gcc.target/powerpc/sse4_1-pinsrq.c: New test.
---
 .../gcc.target/powerpc/sse4_1-pinsrb.c        | 110 ++++++++++++++++++
 .../gcc.target/powerpc/sse4_1-pinsrd.c        |  73 ++++++++++++
 .../gcc.target/powerpc/sse4_1-pinsrq.c        |  67 +++++++++++
 3 files changed, 250 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrb.c
 create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrd.c
 create mode 100644 gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrq.c

Comments

Segher Boessenkool Sept. 24, 2020, 11:25 p.m. UTC | #1 
On Wed, Sep 23, 2020 at 05:12:45PM -0500, Paul A. Clarke wrote:
> Copied from gcc.target/i386.

Okay for trunk then.  Thanks!

(I peeked, it is just fine ;-) )


Segher
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrb.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrb.c
new file mode 100644
index 00000000000..4fa5e83ce7c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrb.c
@@ -0,0 +1,110 @@ 
+/* { dg-do run } */
+/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */
+/* { dg-require-effective-target p8vector_hw } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define msk0 0x00
+#define msk1 0x01
+#define msk2 0x02
+#define msk3 0x03
+#define msk4 0x04
+#define msk5 0x05
+#define msk6 0x06
+#define msk7 0x07
+#define msk8 0x08
+#define msk9 0x09
+#define mskA 0x0A
+#define mskB 0x0B
+#define mskC 0x0C
+#define mskD 0x0D
+#define mskE 0x0E
+#define mskF 0x0F
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+      unsigned char c[16];
+    } res [16], val, tmp;
+  int masks[16];
+  unsigned char ins[4] = { 3, 4, 5, 6 };
+  int i;
+
+  val.i[0] = 0x35251505;
+  val.i[1] = 0x75655545;
+  val.i[2] = 0xB5A59585;
+  val.i[3] = 0xF5E5D5C5;
+
+  /* Check pinsrb imm8, r32, xmm.  */
+  res[0].x = _mm_insert_epi8 (val.x, ins[0], msk0);
+  res[1].x = _mm_insert_epi8 (val.x, ins[0], msk1);
+  res[2].x = _mm_insert_epi8 (val.x, ins[0], msk2);
+  res[3].x = _mm_insert_epi8 (val.x, ins[0], msk3);
+  res[4].x = _mm_insert_epi8 (val.x, ins[0], msk4);
+  res[5].x = _mm_insert_epi8 (val.x, ins[0], msk5);
+  res[6].x = _mm_insert_epi8 (val.x, ins[0], msk6);
+  res[7].x = _mm_insert_epi8 (val.x, ins[0], msk7);
+  res[8].x = _mm_insert_epi8 (val.x, ins[0], msk8);
+  res[9].x = _mm_insert_epi8 (val.x, ins[0], msk9);
+  res[10].x = _mm_insert_epi8 (val.x, ins[0], mskA);
+  res[11].x = _mm_insert_epi8 (val.x, ins[0], mskB);
+  res[12].x = _mm_insert_epi8 (val.x, ins[0], mskC);
+  res[13].x = _mm_insert_epi8 (val.x, ins[0], mskD);
+  res[14].x = _mm_insert_epi8 (val.x, ins[0], mskE);
+  res[15].x = _mm_insert_epi8 (val.x, ins[0], mskF);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+  masks[2] = msk2;
+  masks[3] = msk3;
+  masks[4] = msk4;
+  masks[5] = msk5;
+  masks[6] = msk6;
+  masks[7] = msk7;
+  masks[8] = msk8;
+  masks[9] = msk9;
+  masks[10] = mskA;
+  masks[11] = mskB;
+  masks[12] = mskC;
+  masks[13] = mskD;
+  masks[14] = mskE;
+  masks[15] = mskF;
+
+  for (i = 0; i < 16; i++)
+    {
+      tmp.x = val.x;
+      tmp.c[masks[i]] = ins[0];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+    
+  /* Check pinsrb imm8, m8, xmm.  */
+  for (i = 0; i < 16; i++)
+    {
+      res[i].x = _mm_insert_epi8 (val.x, ins[i % 4], msk0);
+      masks[i] = msk0;
+    }
+
+  for (i = 0; i < 16; i++)
+    {
+      tmp.x = val.x;
+      tmp.c[masks[i]] = ins[i % 4];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrd.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrd.c
new file mode 100644
index 00000000000..0bec936d074
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrd.c
@@ -0,0 +1,73 @@ 
+/* { dg-do run } */
+/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */
+/* { dg-require-effective-target p8vector_hw } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define msk0 0x00
+#define msk1 0x01
+#define msk2 0x02
+#define msk3 0x03
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+    } res [4], val, tmp;
+  static unsigned int ins[4] = { 3, 4, 5, 6 };
+  int masks[4];
+  int i;
+
+  val.i[0] = 55;
+  val.i[1] = 55;
+  val.i[2] = 55;
+  val.i[3] = 55;
+
+  /* Check pinsrd imm8, r32, xmm.  */
+  res[0].x = _mm_insert_epi32 (val.x, ins[0], msk0);
+  res[1].x = _mm_insert_epi32 (val.x, ins[0], msk1);
+  res[2].x = _mm_insert_epi32 (val.x, ins[0], msk2);
+  res[3].x = _mm_insert_epi32 (val.x, ins[0], msk3);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+  masks[2] = msk2;
+  masks[3] = msk3;
+
+  for (i = 0; i < 4; i++)
+    {
+      tmp.x = val.x;
+      tmp.i[masks[i]] = ins[0];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+    
+  /* Check pinsrd imm8, m32, xmm.  */
+  for (i = 0; i < 4; i++)
+    {
+      res[i].x = _mm_insert_epi32 (val.x, ins[i], msk0);
+      masks[i] = msk0;
+    }
+
+  for (i = 0; i < 4; i++)
+    {
+      tmp.x = val.x;
+      tmp.i[masks[i]] = ins[i];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrq.c b/gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrq.c
new file mode 100644
index 00000000000..395c20e663d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sse4_1-pinsrq.c
@@ -0,0 +1,67 @@ 
+/* { dg-do run } */
+/* { dg-options "-O2 -mpower8-vector -Wno-psabi" } */
+/* { dg-require-effective-target p8vector_hw } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define msk0 0x00
+#define msk1 0x01
+
+static void
+__attribute__((noinline))
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      unsigned long long ll[2];
+    } res [4], val, tmp;
+  int masks[4];
+  static unsigned long long ins[2] =
+    { 0xAABBAABBAABBAABBLL, 0xCCDDCCDDCCDDCCDDLL };
+  int i;
+
+  val.ll[0] = 0x0807060504030201LL;
+  val.ll[1] = 0x100F0E0D0C0B0A09LL;
+
+  /* Check pinsrq imm8, r64, xmm.  */
+  res[0].x = _mm_insert_epi64 (val.x, ins[0], msk0);
+  res[1].x = _mm_insert_epi64 (val.x, ins[0], msk1);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+
+  for (i = 0; i < 2; i++)
+    {
+      tmp.x = val.x;
+      tmp.ll[masks[i]] = ins[0];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+    
+  /* Check pinsrq imm8, m64, xmm.  */
+  for (i = 0; i < 2; i++)
+    {
+      res[i].x = _mm_insert_epi64 (val.x, ins[i], msk0);
+      masks[i] = msk0;
+    }
+
+  for (i = 0; i < 2; i++)
+    {
+      tmp.x = val.x;
+      tmp.ll[masks[i]] = ins[i];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+}