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Fri, 08 May 2020 13:12:20 +0000 Received: from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com [9.57.199.107]) by b01cxnp22033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 048DCJEH40304926 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 8 May 2020 13:12:19 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 64FF7124053; Fri, 8 May 2020 13:12:19 +0000 (GMT) Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 41908124058; Fri, 8 May 2020 13:12:19 +0000 (GMT) Received: from localhost (unknown [9.40.194.84]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTP; Fri, 8 May 2020 13:12:19 +0000 (GMT) To: gcc-patches@gcc.gnu.org Subject: [PATCH] rs6000: Add vcfuged instruction Date: Fri, 8 May 2020 08:12:14 -0500 Message-Id: <20200508131214.22871-1-wschmidt@linux.ibm.com> X-Mailer: git-send-email 2.17.1 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.216, 18.0.676 definitions=2020-05-08_12:2020-05-07, 2020-05-08 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 spamscore=0 clxscore=1015 priorityscore=1501 suspectscore=1 bulkscore=0 lowpriorityscore=0 malwarescore=0 mlxscore=0 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2005080116 X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Bill Schmidt via Gcc-patches From: Bill Schmidt Reply-To: Bill Schmidt Cc: dje.gcc@gmail.com, segher@kernel.crashing.org Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" From: Kelvin Nilsen Add the new vector centrifuge-doubleword instruction and built-in function access. Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no regressions. Is this okay for master? Thanks, Bill [gcc] 2020-05-08 Kelvin Nilsen * config/rs6000/altivec.h (vec_cfuge): New #define. * config/rs6000/altivec.md (UNSPEC_VCFUGED): New constant. (vcfuged): New insn. * config/rs6000/rs6000-builtin.def (__builtin_altivec_vcfuged): New built-in function. * config/rs6000/rs6000-call.c (builtin_function_type): Add handling for FUTURE_BUILTIN_VCFUGED case. * doc/extend.texi (PowerPC AltiVec Built-in Functions Available for a Future Architecture): Add description of vec_cfuge built-in function. [gcc/testsuite] 2020-05-08 Kelvin Nilsen * gcc.target/powerpc/vec-cfuged-0.c: New test. * gcc.target/powerpc/vec-cfuged-1.c: New test. --- gcc/config/rs6000/altivec.h | 1 + gcc/config/rs6000/altivec.md | 10 +++ gcc/config/rs6000/rs6000-builtin.def | 1 + gcc/config/rs6000/rs6000-call.c | 1 + gcc/doc/extend.texi | 9 +++ .../gcc.target/powerpc/vec-cfuged-0.c | 61 +++++++++++++++++++ .../gcc.target/powerpc/vec-cfuged-1.c | 60 ++++++++++++++++++ 7 files changed, 143 insertions(+) create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-cfuged-0.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-cfuged-1.c diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index b6ecad6911d..0ecd961485b 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -693,6 +693,7 @@ __altivec_scalar_pred(vec_any_nle, #define vec_ctzm(a, b) __builtin_altivec_vctzdm (a, b) #define vec_pdep(a, b) __builtin_altivec_vpdepd (a, b) #define vec_pext(a, b) __builtin_altivec_vpextd (a, b) +#define vec_cfuge(a, b) __builtin_altivec_vcfuged (a, b) /* Overloaded built-in functions for future architecture. */ #define vec_gnb(a, b) __builtin_vec_gnb (a, b) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 7cebb58331e..1400724fb58 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -160,6 +160,7 @@ (define_c_enum "unspec" UNSPEC_BCD_OVERFLOW UNSPEC_VRLMI UNSPEC_VRLNM + UNSPEC_VCFUGED UNSPEC_VCLZDM UNSPEC_VCTZDM UNSPEC_VGNB @@ -4101,6 +4102,15 @@ (define_insn "*bcd_test2" "bcd. %0,%1,%2,%3" [(set_attr "type" "vecsimple")]) +(define_insn "vcfuged" + [(set (match_operand:V2DI 0 "altivec_register_operand" "=v") + (unspec:V2DI [(match_operand:V2DI 1 "altivec_register_operand" "v") + (match_operand:V2DI 2 "altivec_register_operand" "v")] + UNSPEC_VCFUGED))] + "TARGET_FUTURE" + "vcfuged %0,%1,%2" + [(set_attr "type" "vecsimple")]) + (define_insn "vclzdm" [(set (match_operand:V2DI 0 "altivec_register_operand" "=v") (unspec:V2DI [(match_operand:V2DI 1 "altivec_register_operand" "v") diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index afc8487515f..9d80d03fe50 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -2577,6 +2577,7 @@ BU_P9_OVERLOAD_2 (CMPEQB, "byte_in_set") BU_FUTURE_MISC_2 (CFUGED, "cfuged", CONST, cfuged) /* Future architecture vector built-ins. */ +BU_FUTURE_V_2 (VCFUGED, "vcfuged", CONST, vcfuged) BU_FUTURE_V_2 (VCLZDM, "vclzdm", CONST, vclzdm) BU_FUTURE_V_2 (VCTZDM, "vctzdm", CONST, vctzdm) BU_FUTURE_V_2 (VPDEPD, "vpdepd", CONST, vpdepd) diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c index 952f17c6854..c3ba6b93c46 100644 --- a/gcc/config/rs6000/rs6000-call.c +++ b/gcc/config/rs6000/rs6000-call.c @@ -12951,6 +12951,7 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0, case P8V_BUILTIN_ORC_V4SI_UNS: case P8V_BUILTIN_ORC_V2DI_UNS: case P8V_BUILTIN_ORC_V1TI_UNS: + case FUTURE_BUILTIN_VCFUGED: case FUTURE_BUILTIN_VCLZDM: case FUTURE_BUILTIN_VCTZDM: case FUTURE_BUILTIN_VGNB: diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 8b5a51a6973..f7b30c7ead7 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -20719,6 +20719,15 @@ PowerPC family of processors, starting with a hypothetical CPU which may or may not be available in the future (@option{-mcpu=future}) or later: + +@smallexample +@exdent vector unsigned long long int +@exdent vec_cfuge (vector unsigned long long int, vector unsigned long long int) +@end smallexample +Perform a vector centrifuge operation, as if implemented by the Future +@code{vcfuged} instruction. +@findex vec_cfuge + @smallexample @exdent vector unsigned long long int @exdent vec_clzm (vector unsigned long long int, vector unsigned long long int) diff --git a/gcc/testsuite/gcc.target/powerpc/vec-cfuged-0.c b/gcc/testsuite/gcc.target/powerpc/vec-cfuged-0.c new file mode 100644 index 00000000000..74528a4f762 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-cfuged-0.c @@ -0,0 +1,61 @@ +/* { dg-do compile } */ +/* { dg-options "-mdejagnu-cpu=future" } */ + +#include + +extern void abort (void); + +vector unsigned long long int +do_vec_cfuge (vector unsigned long long int source, + vector unsigned long long int mask) +{ + return vec_cfuge (source, mask); +} + +int +vectors_equal (vector unsigned long long int a, + vector unsigned long long int b) +{ + return (a[0] == b[0]) && (a[1] == b[1]); +} + +int main (int argc, char *argv []) +{ + vector unsigned long long int source_a = { 0xa5f07e3cull, 0x7e3ca5f0ull }; + vector unsigned long long int source_b = { 0x3ca5f07eull, 0x5a0fe7c3ull }; + + vector unsigned long long int mask_a = { 0xffff0000ull, 0x0000ffffull }; + vector unsigned long long int mask_b = { 0x0f0f0f0full, 0xf0f0f0f0ull }; + + /* See cfuged-0.c for derivation of expected results. + + result_aa [0] is compute (source [0], mask [0]; + result_aa [1] is compute (source [1], mask [1]. + + result_ab [0] is compute (source [0], mask [2]; + result_ab [1] is compute (source [1], mask [3]. + + result_ba [0] is compute (source [2], mask [0]; + result_ba [1] is compute (source [3], mask [1]. + + result_bb [0] is compute (source [2], mask [2]; + result_bb [1] is compute (source [3], mask [3]. */ + + vector unsigned long long int result_aa = { 0x7e3ca5f0ull, 0x7e3ca5f0ull }; + vector unsigned long long int result_ab = { 0xaf7350ecull, 0xec5073afull }; + vector unsigned long long int result_ba = { 0xf07e3ca5ull, 0x5a0fe7c3ull }; + vector unsigned long long int result_bb = { 0x3af7c50eull, 0xaf7350ecull }; + + if (!vectors_equal (do_vec_cfuge (source_a, mask_a), result_aa)) + abort (); + if (!vectors_equal (do_vec_cfuge (source_a, mask_b), result_ab)) + abort (); + if (!vectors_equal (do_vec_cfuge (source_b, mask_a), result_ba)) + abort (); + if (!vectors_equal (do_vec_cfuge (source_b, mask_b), result_bb)) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler {\mvcfuged\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-cfuged-1.c b/gcc/testsuite/gcc.target/powerpc/vec-cfuged-1.c new file mode 100644 index 00000000000..2c8013544e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-cfuged-1.c @@ -0,0 +1,60 @@ +/* { dg-do run } */ +/* { dg-require-effective-target powerpc_future_hw } */ +/* { dg-options "-mdejagnu-cpu=future" } */ + +#include + +extern void abort (void); + +vector unsigned long long int +do_vec_cfuge (vector unsigned long long int source, + vector unsigned long long int mask) +{ + return vec_cfuge (source, mask); +} + +int +vectors_equal (vector unsigned long long int a, + vector unsigned long long int b) +{ + return (a[0] == b[0]) && (a[1] == b[1]); +} + +int main (int argc, char *argv []) +{ + vector unsigned long long int source_a = { 0xa5f07e3cull, 0x7e3ca5f0ull }; + vector unsigned long long int source_b = { 0x3ca5f07eull, 0x5a0fe7c3ull }; + + vector unsigned long long int mask_a = { 0xffff0000ull, 0x0000ffffull }; + vector unsigned long long int mask_b = { 0x0f0f0f0full, 0xf0f0f0f0ull }; + + /* See cfuged-0.c for derivation of expected results. + + result_aa [0] is compute (source [0], mask [0]; + result_aa [1] is compute (source [1], mask [1]. + + result_ab [0] is compute (source [0], mask [2]; + result_ab [1] is compute (source [1], mask [3]. + + result_ba [0] is compute (source [2], mask [0]; + result_ba [1] is compute (source [3], mask [1]. + + result_bb [0] is compute (source [2], mask [2]; + result_bb [1] is compute (source [3], mask [3]. */ + + vector unsigned long long int result_aa = { 0x7e3ca5f0ull, 0x7e3ca5f0ull }; + vector unsigned long long int result_ab = { 0xaf7350ecull, 0xec5073afull }; + vector unsigned long long int result_ba = { 0xf07e3ca5ull, 0x5a0fe7c3ull }; + vector unsigned long long int result_bb = { 0x3af7c50eull, 0xaf7350ecull }; + + if (!vectors_equal (do_vec_cfuge (source_a, mask_a), result_aa)) + abort (); + if (!vectors_equal (do_vec_cfuge (source_a, mask_b), result_ab)) + abort (); + if (!vectors_equal (do_vec_cfuge (source_b, mask_a), result_ba)) + abort (); + if (!vectors_equal (do_vec_cfuge (source_b, mask_b), result_bb)) + abort (); + + return 0; +}