Message ID | 20200311165823.53368-1-kito.cheng@sifive.com |
---|---|
State | New |
Headers | show |
Series | [committed] RISC-V: Fix testsuite regression due to recent IRA changes. | expand |
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 11061adaf18..e2442fba35a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2020-03-11 Kito Cheng <kito.cheng@sifive.com> + + * gcc.target/riscv/interrupt-2.c: Update testcase and expected output. + 2020-03-11 Richard Biener <rguenther@suse.de> * gcc.dg/torture/20200311-1.c: New testcase. diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-2.c b/gcc/testsuite/gcc.target/riscv/interrupt-2.c index 9559007e4ae..82e3fb24e81 100644 --- a/gcc/testsuite/gcc.target/riscv/interrupt-2.c +++ b/gcc/testsuite/gcc.target/riscv/interrupt-2.c @@ -8,10 +8,6 @@ foo2 (void) INTERRUPT_FLAG = 0; extern volatile int COUNTER; -#ifdef __riscv_atomic - __atomic_fetch_add (&COUNTER, 1, __ATOMIC_RELAXED); -#else COUNTER++; -#endif } /* { dg-final { scan-assembler-times "s\[wd\]\ta\[0-7\],\[0-9\]+\\(sp\\)" 2 } } */