From patchwork Mon Feb 10 15:51:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Earnshaw X-Patchwork-Id: 1235874 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-519243-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha1 header.s=default header.b=gGDq1+UK; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48GVlj5kQ8z9sP7 for ; Tue, 11 Feb 2020 02:52:16 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:in-reply-to :content-type; q=dns; s=default; b=yXbGjVp8BNEo7X/LRHtB/gWhknUUT Wk0yhP6pji/o8/NHP0dkeUOpJQgzcslF719LukLhdcjIk7UBTHEoNHeTchor7j4n NBypCo4TZzb5j5nCVDBgS7dgTSVANugw/jKIH+UIqpO1OsWu00+SpTRWFPX9oHLJ u3mOwMhn3YQ+iw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:in-reply-to :content-type; s=default; bh=9WDE89of8GGqpAXQQSQ+R8iiIF4=; b=gGD q1+UKJmjdDk0oAMWYZYAzxOeTOht5J2r99hwHmXoxVveQ71wynThhJ2rYLy3zTRt OXUt7R8TMav5tyKDX7thFWyF/pGA4F4edrCNcZsZRlNjapfclzN1hgII2n9G7F/T 566GmWbion6Ahd47rhsGWEq9mdluCGlXZZ45jNn8= Received: (qmail 20233 invoked by alias); 10 Feb 2020 15:52:08 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 20214 invoked by uid 89); 10 Feb 2020 15:52:07 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-13.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.1 spammy=HX-Languages-Length:1729, states X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 10 Feb 2020 15:52:06 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1A2111FB; Mon, 10 Feb 2020 07:52:05 -0800 (PST) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.78.81]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 490A03F68F; Mon, 10 Feb 2020 07:52:04 -0800 (PST) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw , Jakub Jelinek , Ramana Radhakrishnan , Kyrylo Tkachov Subject: [PATCH] arm: correct constraints on movsi_compare0 [PR91913] Date: Mon, 10 Feb 2020 15:51:56 +0000 Message-Id: <20200210155156.6047-1-rearnsha@arm.com> MIME-Version: 1.0 In-Reply-To: <20200201083040.GZ17695@tucnak> The peephole that detects a mov of one register to another followed by a comparison of the original register against zero is only used in Arm state; but the instruction that matches this is generic to all 32-bit compilation states. That instruction lacks support for SP which is permitted in Arm state, but has restrictions in Thumb2 code. This patch fixes the problem by allowing SP when in ARM state for all registers; in Thumb state it allows SP only as a source when the register really is copied to another target. * config/arm/arm.md (movsi_compare0): Allow SP as a source register in Thumb state and also as a destination in Arm state. Add T16 variants. --- gcc/config/arm/arm.md | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 5baf82d2ad6..ab277996462 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -6627,16 +6627,21 @@ (define_expand "builtin_setjmp_receiver" (define_insn "*movsi_compare0" [(set (reg:CC CC_REGNUM) - (compare:CC (match_operand:SI 1 "s_register_operand" "0,r") + (compare:CC (match_operand:SI 1 "s_register_operand" "0,0,l,rk,rk") (const_int 0))) - (set (match_operand:SI 0 "s_register_operand" "=r,r") + (set (match_operand:SI 0 "s_register_operand" "=l,rk,l,r,rk") (match_dup 1))] "TARGET_32BIT" "@ cmp%?\\t%0, #0 + cmp%?\\t%0, #0 + subs%?\\t%0, %1, #0 + subs%?\\t%0, %1, #0 subs%?\\t%0, %1, #0" [(set_attr "conds" "set") - (set_attr "type" "alus_imm,alus_imm")] + (set_attr "arch" "t2,*,t2,t2,a") + (set_attr "type" "alus_imm") + (set_attr "length" "2,4,2,4,4")] ) ;; Subroutine to store a half word from a register into memory.