| Message ID | 20200210155156.6047-1-rearnsha@arm.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm: correct constraints on movsi_compare0 [PR91913] | expand |
On 10/02/2020 15:51, Richard Earnshaw wrote: > > The peephole that detects a mov of one register to another followed by > a comparison of the original register against zero is only used in Arm > state; but the instruction that matches this is generic to all 32-bit > compilation states. That instruction lacks support for SP which is > permitted in Arm state, but has restrictions in Thumb2 code. > > This patch fixes the problem by allowing SP when in ARM state for all > registers; in Thumb state it allows SP only as a source when the > register really is copied to another target. > > * config/arm/arm.md (movsi_compare0): Allow SP as a source register > in Thumb state and also as a destination in Arm state. Add T16 > variants. > --- > gcc/config/arm/arm.md | 11 ++++++++--- > 1 file changed, 8 insertions(+), 3 deletions(-) > I've now backported this (along with Jakub's test) to gcc-8 and gcc-9. R.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 5baf82d2ad6..ab277996462 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -6627,16 +6627,21 @@ (define_expand "builtin_setjmp_receiver" (define_insn "*movsi_compare0" [(set (reg:CC CC_REGNUM) - (compare:CC (match_operand:SI 1 "s_register_operand" "0,r") + (compare:CC (match_operand:SI 1 "s_register_operand" "0,0,l,rk,rk") (const_int 0))) - (set (match_operand:SI 0 "s_register_operand" "=r,r") + (set (match_operand:SI 0 "s_register_operand" "=l,rk,l,r,rk") (match_dup 1))] "TARGET_32BIT" "@ cmp%?\\t%0, #0 + cmp%?\\t%0, #0 + subs%?\\t%0, %1, #0 + subs%?\\t%0, %1, #0 subs%?\\t%0, %1, #0" [(set_attr "conds" "set") - (set_attr "type" "alus_imm,alus_imm")] + (set_attr "arch" "t2,*,t2,t2,a") + (set_attr "type" "alus_imm") + (set_attr "length" "2,4,2,4,4")] ) ;; Subroutine to store a half word from a register into memory.