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[v2,1/6] aarch64: Add "c" constraint

Message ID 20191114100716.28827-2-richard.henderson@linaro.org
State New
Headers show
Series Implement asm flag outputs for arm + aarch64 | expand

Commit Message

Richard Henderson Nov. 14, 2019, 10:07 a.m. UTC 
Mirror arm in letting "c" match the condition code register.

	* config/aarch64/constraints.md (c): New constraint.
---
 gcc/config/aarch64/constraints.md | 4 ++++
 1 file changed, 4 insertions(+)
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Patch

diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md
index d0c3dd5bc1f..b9e5d13e851 100644
--- a/gcc/config/aarch64/constraints.md
+++ b/gcc/config/aarch64/constraints.md
@@ -39,6 +39,10 @@ 
 (define_register_constraint "y" "FP_LO8_REGS"
   "Floating point and SIMD vector registers V0 - V7.")
 
+(define_constraint "c"
+ "@internal The condition code register."
+  (match_operand 0 "cc_register"))
+
 (define_constraint "I"
  "A constant that can be used with an ADD operation."
  (and (match_code "const_int")