[12/29,arm] Implement negscc using SBC when appropriate.

Message ID	20191018194900.34795-13-Richard.Earnshaw@arm.com
State	New
Headers	show Return-Path: <gcc-patches-return-511318-incoming=patchwork.ozlabs.org@gcc.gnu.org> DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; q=dns; s=default; b=HNacEcNlSisU5+Xh hI7DkhfGd236rIzxluVsyv8AD+8gaOhjVHJP8nfUqbyVVQI8ez7S0E07Foy/1xHa LWTBuD8gYf5afdBVLfuuEUx3YTuLgCITX7CwqVkvUjaHgOufcytQfTX/MCOAT18P eJn79oe7eM1YZyMyNfGsA46W8T0= Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org From: Richard Earnshaw <Richard.Earnshaw@arm.com> To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw <Richard.Earnshaw@arm.com> Subject: [PATCH 12/29] [arm] Implement negscc using SBC when appropriate. Date: Fri, 18 Oct 2019 20:48:43 +0100 Message-Id: <20191018194900.34795-13-Richard.Earnshaw@arm.com> In-Reply-To: <20191018194900.34795-1-Richard.Earnshaw@arm.com> References: <20191018194900.34795-1-Richard.Earnshaw@arm.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------2.17.1"
Series	Rewrite DImode arithmetic support \| expand [00/29,arm] Rewrite DImode arithmetic support [01/29,arm] Rip out DImode addition and subtraction splits. [02/29,arm] Perform early splitting of adddi3. [03/29,arm] Early split zero- and sign-extension [04/29,arm] Rewrite addsi3_carryin_shift_<optab> in canonical form [05/29,arm] fix constraints on addsi3_carryin_alt2 [06/29,arm] Early split subdi3 [07/29,arm] Remove redundant DImode subtract patterns [08/29,arm] Introduce arm_carry_operation [09/29,arm] Correctly cost addition with a carry-in [10/29,arm] Correct cost calculations involving borrow for subtracts. [11/29,arm] Reduce cost of insns that are simple reg-reg moves. [12/29,arm] Implement negscc using SBC when appropriate. [13/29,arm] Add alternative canonicalizations for subtract-with-carry + shift [14/29,arm] Early split simple DImode equality comparisons [15/29,arm] Improve handling of DImode comparisions against constants. [16/29,arm] early split most DImode comparison operations. [17/29,arm] Handle some constant comparisons using rsbs+rscs [18/29,arm] Cleanup dead code - old support for DImode comparisons [19/29,arm] Handle immediate values in uaddvsi4 [20/29,arm] Early expansion of uaddvdi4. [21/29,arm] Improve code generation for addvsi4. [22/29,arm] Allow the summation result of signed add-with-overflow to be discarded. [23/29,arm] Early split addvdi4 [24/29,arm] Improve constant handling for usubvsi4. [25/29,arm] Early expansion of usubvdi4. [26/29,arm] Improve constant handling for subvsi4. [27/29,arm] Early expansion of subvdi4 [28/29,arm] Improvements to negvsi4 and negvdi4. [29/29,arm] Fix testsuite nit when compiling for thumb2

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20191018194900.34795-13-Richard.Earnshaw@arm.com

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Subject: [PATCH 12/29] [arm] Implement negscc using SBC when appropriate.
Date: Fri, 18 Oct 2019 20:48:43 +0100
Message-Id: <20191018194900.34795-13-Richard.Earnshaw@arm.com>
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Series

Rewrite DImode arithmetic support | expand

Commit Message

Richard Earnshaw (lists) Oct. 18, 2019, 7:48 p.m. UTC

When the carry flag is appropriately set by a comprison, negscc
patterns can expand into a simple SBC of a register with itself.  This
means we can convert two conditional instructions into a single
non-conditional instruction.  Furthermore, in Thumb2 we can avoid the
need for an IT instruction as well.  This patch also fixes the remaining
testcase that we initially XFAILed in the first patch of this series.

gcc:
	* config/arm/arm.md (negscc_borrow): New pattern.
	(mov_negscc): Don't split if the insn would match negscc_borrow.
	* config/arm/thumb2.md (thumb2_mov_negscc): Likewise.
	(thumb2_mov_negscc_strict_it): Likewise.

testsuite:
	* gcc.target/arm/negdi-3.c: Remove XFAIL markers.
---
 gcc/config/arm/arm.md                  | 14 ++++++++++++--
 gcc/config/arm/thumb2.md               |  8 ++++++--
 gcc/testsuite/gcc.target/arm/negdi-3.c |  8 ++++----
 3 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index f53dbc27207..74f417fbe4b 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -6612,13 +6612,23 @@  (define_insn_and_split "*mov_scc"
    (set_attr "type" "multiple")]
 )
 
+(define_insn "*negscc_borrow"
+  [(set (match_operand:SI 0 "s_register_operand" "=r")
+	(neg:SI (match_operand:SI 1 "arm_borrow_operation" "")))]
+  "TARGET_32BIT"
+  "sbc\\t%0, %0, %0"
+  [(set_attr "conds" "use")
+   (set_attr "length" "4")
+   (set_attr "type" "adc_reg")]
+)
+
 (define_insn_and_split "*mov_negscc"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
 	(neg:SI (match_operator:SI 1 "arm_comparison_operator_mode"
 		 [(match_operand 2 "cc_register" "") (const_int 0)])))]
-  "TARGET_ARM"
+  "TARGET_ARM && !arm_borrow_operation (operands[1], SImode)"
   "#"   ; "mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
-  "TARGET_ARM"
+  "&& true"
   [(set (match_dup 0)
         (if_then_else:SI (match_dup 1)
                          (match_dup 3)
diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index 6ccc875e2b4..8d0b6be9205 100644
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -368,7 +368,9 @@  (define_insn_and_split "*thumb2_mov_negscc"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
 	(neg:SI (match_operator:SI 1 "arm_comparison_operator_mode"
 		 [(match_operand 2 "cc_register" "") (const_int 0)])))]
-  "TARGET_THUMB2 && !arm_restrict_it"
+  "TARGET_THUMB2
+   && !arm_restrict_it
+   && !arm_borrow_operation (operands[1], SImode)"
   "#"   ; "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
   "&& true"
   [(set (match_dup 0)
@@ -387,7 +389,9 @@  (define_insn_and_split "*thumb2_mov_negscc_strict_it"
   [(set (match_operand:SI 0 "low_register_operand" "=l")
 	(neg:SI (match_operator:SI 1 "arm_comparison_operator_mode"
 		 [(match_operand 2 "cc_register" "") (const_int 0)])))]
-  "TARGET_THUMB2 && arm_restrict_it"
+  "TARGET_THUMB2
+   && arm_restrict_it
+   && !arm_borrow_operation (operands[1], SImode)"
   "#"   ; ";mvn\\t%0, #0 ;it\\t%D1\;mov%D1\\t%0, #0\"
   "&& reload_completed"
   [(set (match_dup 0)
diff --git a/gcc/testsuite/gcc.target/arm/negdi-3.c b/gcc/testsuite/gcc.target/arm/negdi-3.c
index 3f6f2d1c2bb..76ddf49fc0d 100644
--- a/gcc/testsuite/gcc.target/arm/negdi-3.c
+++ b/gcc/testsuite/gcc.target/arm/negdi-3.c
@@ -11,7 +11,7 @@  Expected output:
         rsbs    r0, r0, #0
         sbc     r1, r1, r1
 */
-/* { dg-final { scan-assembler-times "rsb" 1 { xfail *-*-* } } } */
-/* { dg-final { scan-assembler-times "sbc" 1 { xfail *-*-* } } } */
-/* { dg-final { scan-assembler-times "mov" 0 { xfail *-*-* } } } */
-/* { dg-final { scan-assembler-times "rsc" 0 { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-times "rsb" 1 } } */
+/* { dg-final { scan-assembler-times "sbc" 1 } } */
+/* { dg-final { scan-assembler-times "mov" 0 } } */
+/* { dg-final { scan-assembler-times "rsc" 0 } } */

[12/29,arm] Implement negscc using SBC when appropriate.

Commit Message

Patch