From patchwork Tue Mar 19 22:35:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 1058741 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-498154-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="Kz+Fn+dS"; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="FZigbs+Q"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44P7DC1gSSz9sNH for ; Wed, 20 Mar 2019 09:35:19 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=sEGWgZKSB0MI lY7WTJGzOZ9lZFlcvt+oc5mNc0h2Syzm1Ru/6FO2jqLW9MNurrF2lLepxU7C727n hphQy29wMvaEZLlqLk+bO9p6sRv2VTtK8Kj46hHf1tMjZWUmnWyoBcgnfAq/q9PB znNu1YQGsbwdy2OBfqB2X3+6w6PlDPk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=W9xpmK877TjAMPEHeE 7+bGYYcwc=; b=Kz+Fn+dSAfzI9h4krV52UHyq5QfYxdfNQgAx4Iw9/FA39WJLto okFyzhGmGjsZN1raVbn0HZ4uTTFwA0qFRYUiVvH+sxy6OGdTe6/bh/AOPeWyxD0D oku34Q6xS/tsLsfky3sISHGkOpvaKifbQRfxl6p/V1OGJ0e9ADXtBFP6E= Received: (qmail 24522 invoked by alias); 19 Mar 2019 22:35:13 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 24514 invoked by uid 89); 19 Mar 2019 22:35:12 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-12.3 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_STOCKGEN, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=accessed, tree_to_uhwi, HX-Received:8a92, H*r:sk:mail-pg X-HELO: mail-pg1-f176.google.com Received: from mail-pg1-f176.google.com (HELO mail-pg1-f176.google.com) (209.85.215.176) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 19 Mar 2019 22:35:10 +0000 Received: by mail-pg1-f176.google.com with SMTP id r124so222692pgr.3 for ; Tue, 19 Mar 2019 15:35:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id; bh=QdNJMK/+nntwf+tf2FWPapG83r5h/jokrRK4CiPEjw0=; b=FZigbs+QH7Ade2m63GRiG6NEUH9cq7s6WiAOQTQawYWFE1KGJP86JHKINJ++MmXMMd NIOgdSKG/SJG4XqOCqbfaNnvNoHc+Bn6VOdOTp3dcAgIxVgC5aEB0CFV5MQ6DU7Flitz Qw/+LhDr+5y9708s2ErgOe3OO+w43LBTpkpiMBELBW1nzIlS0rZn+ZSBhneAhDNwmoZl 9FlfOlMiqMicTJmePsWv++Pmq0/0QYGydoBPVwEK/sJDCPWP2E36vClhYawXkjdtFXQ4 q5sC7fUtArXD+GYcF5NRcUVn+Sys8b9a2o9d5DDXmBsknpw9uLTbHYGxL8hsUIlwrr31 b81Q== Received: from rohan.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id k72sm104600pfb.122.2019.03.19.15.35.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Mar 2019 15:35:08 -0700 (PDT) From: Jim Wilson To: gcc-patches@gcc.gnu.org Cc: Jim Wilson Subject: [PATCH] RISC-V: Fix %lo overflow with BLKmode references. Date: Tue, 19 Mar 2019 15:35:04 -0700 Message-Id: <20190319223504.15802-1-jimw@sifive.com> This fixes the bug reported in PR 89411 where we accidentally generated a %lo with an offset that overflowed at link time if the symbol was allocated to an address just below the 2KB limit for %lo. This solves the problem by checking for BLKmode references, pulling out the SYMBOL_REF_DECL, and then getting size and alignment from the decl instead of from the mode. Tested with 32-bit/64-bit elf/linux cross builds and checks. There were no regressions. The new testcase fails without the patch and works with the patch. Committed. Jim gcc/ PR target/89411 * config/riscv/riscv.c (riscv_valid_lo_sum_p): New arg x. New locals align, size, offset. Use them to handle a BLKmode reference. Update comment. (riscv_classify_address): Pass info->offset to riscv_valid_lo_sum_p. gcc/testsuite/ PR target/89411 * gcc.target/riscv/losum-overflow.c: New test. --- gcc/config/riscv/riscv.c | 43 ++++++++++++++++--- .../gcc.target/riscv/losum-overflow.c | 29 +++++++++++++ 2 files changed, 66 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/losum-overflow.c diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 8e78ab76375..d8446f82b96 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -708,11 +708,15 @@ riscv_split_symbol_type (enum riscv_symbol_type symbol_type) } /* Return true if a LO_SUM can address a value of mode MODE when the - LO_SUM symbol has type SYM_TYPE. */ + LO_SUM symbol has type SYM_TYPE. X is the LO_SUM second operand, which + is used when the mode is BLKmode. */ static bool -riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type, machine_mode mode) +riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type, machine_mode mode, + rtx x) { + int align, size; + /* Check that symbols of type SYMBOL_TYPE can be used to access values of mode MODE. */ if (riscv_symbol_insns (sym_type) == 0) @@ -722,11 +726,38 @@ riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type, machine_mode mode) if (!riscv_split_symbol_type (sym_type)) return false; + /* We can't tell size or alignment when we have BLKmode, so try extracing a + decl from the symbol if possible. */ + if (mode == BLKmode) + { + rtx offset; + + /* Extract the symbol from the LO_SUM operand, if any. */ + split_const (x, &x, &offset); + + /* Might be a CODE_LABEL. We can compute align but not size for that, + so don't bother trying to handle it. */ + if (!SYMBOL_REF_P (x)) + return false; + + /* Use worst case assumptions if we don't have a SYMBOL_REF_DECL. */ + align = (SYMBOL_REF_DECL (x) + ? DECL_ALIGN (SYMBOL_REF_DECL (x)) + : 1); + size = (SYMBOL_REF_DECL (x) && DECL_SIZE (SYMBOL_REF_DECL (x)) + ? tree_to_uhwi (DECL_SIZE (SYMBOL_REF_DECL (x))) + : 2*BITS_PER_WORD); + } + else + { + align = GET_MODE_ALIGNMENT (mode); + size = GET_MODE_BITSIZE (mode); + } + /* We may need to split multiword moves, so make sure that each word can be accessed without inducing a carry. */ - if (GET_MODE_SIZE (mode) > UNITS_PER_WORD - && (!TARGET_STRICT_ALIGN - || GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))) + if (size > BITS_PER_WORD + && (!TARGET_STRICT_ALIGN || size > align)) return false; return true; @@ -772,7 +803,7 @@ riscv_classify_address (struct riscv_address_info *info, rtx x, info->symbol_type = riscv_classify_symbolic_expression (info->offset); return (riscv_valid_base_register_p (info->reg, mode, strict_p) - && riscv_valid_lo_sum_p (info->symbol_type, mode)); + && riscv_valid_lo_sum_p (info->symbol_type, mode, info->offset)); case CONST_INT: /* Small-integer addresses don't occur very often, but they diff --git a/gcc/testsuite/gcc.target/riscv/losum-overflow.c b/gcc/testsuite/gcc.target/riscv/losum-overflow.c new file mode 100644 index 00000000000..9c01c7feb54 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/losum-overflow.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32 -O2 -fno-section-anchors" } */ + +/* Check for %lo overflow. Adding an offset larger than the alignment can + overflow if the data is allocated to an address mod 4KB that is between + 2KB-offset+1 and 2KB-1. */ +typedef long long int int64_t; + +#pragma pack(push) +#pragma pack(1) +struct S0 { + signed f0 : 4; + const volatile int64_t f1; + volatile signed f2 : 1; + signed f3 : 31; + unsigned f4 : 8; + signed f5 : 20; + unsigned f6 : 5; +}; +#pragma pack(pop) + +struct S0 g_3030 = {0,-9L,-0,-22553,7,-841,1}; + +int64_t +sub (void) +{ + return g_3030.f1; +} +/* { dg-final { scan-assembler-not "%lo\\(g_3030\\+4\\)" } } */