From patchwork Wed Oct 10 08:00:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu X-Patchwork-Id: 981744 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-487235-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="jmvwMcci"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="hgc0hgKT"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42VRQM3ztYz9s8F for ; Wed, 10 Oct 2018 19:02:03 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=MghXVpldK+sjgLxSeAIV2D3tLvI/o5y0JE7tJFstYwLqhLcee17VZ pg+Z9AkW+GkVL3AA77E6H0/9Ty5QocM0TMx64gnYPjZU5RK25qP6t/OXkRHct/zq jSMjmYgywPety3HFrxcu+YnaD+bhw1uofFy9Ljxnq51NTjcZxraegM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=L7XYI11etZZVIQhkmK6LOLSo7Lw=; b=jmvwMcciDSUu4hxILBTo v3qhPeqGaSsxFOL8aGxKem+72xlkiDz+VF2hbCEMde7GTLHg2JfRqhvTnfScVV77 dxoj50Tpe5U5UuC39+sXRcWTYaBuD0cMx1IIBrYeXsAzB3V5D9Kzvok44h9nmyqb 18gze+mcgTrDyWmON0SP4jo= Received: (qmail 71642 invoked by alias); 10 Oct 2018 08:01:25 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 70670 invoked by uid 89); 10 Oct 2018 08:00:38 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.8 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=HX-Received:Wed, barrel, norm, H*r:sk:w19-v6s X-HELO: mail-ed1-f46.google.com Received: from mail-ed1-f46.google.com (HELO mail-ed1-f46.google.com) (209.85.208.46) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 10 Oct 2018 08:00:31 +0000 Received: by mail-ed1-f46.google.com with SMTP id w19-v6so4061728eds.1 for ; Wed, 10 Oct 2018 01:00:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jmlzUyLk4tL3nWtwOYhWX9WLUn9vkOXX+Qf8PZ4id0Q=; b=hgc0hgKTlwCNChQ1REt9LAsc7m710yJ4SNyPgA/2L2T3aQy9H4kW2NRWQzqN/Qjdmq RDDwDMo94ZwkP76jFtdx2JO31EJYErMpjSoqBaPTQ8fIw8CjUVnaD84b7eRZyZNmtqsr AuN7WKFHtUJzcblvw+CEFOUmNPcssDsNJGew7SB/lzpOgB12icuRvcvzatoLjrqQtqZF N7JZ7GSKuxorOlUfTaHi7GTi8B5OyRmo6MOJh7q8dII7MetPOcZYeLpevFfhTKoXDUIr Kgm4p1cBrhd/LQRlSOPl3Sp93kZ2iwOsa0ZyfW6sh4abI7qH7d0RDD4DdQI5Zj+Gt5dZ 12CA== Received: from localhost.localdomain ([188.241.79.25]) by smtp.gmail.com with ESMTPSA id a17-v6sm7533362edd.61.2018.10.10.01.00.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 10 Oct 2018 01:00:27 -0700 (PDT) From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Cc: andrew.burgess@embecosm.com, fbedard@synopsys.com, claziss@synopsys.com Subject: [PATCH 1/6] [ARC] Remove non standard funcions calls. Date: Wed, 10 Oct 2018 11:00:11 +0300 Message-Id: <20181010080016.12317-2-claziss@gmail.com> In-Reply-To: <20181010080016.12317-1-claziss@gmail.com> References: <20181010080016.12317-1-claziss@gmail.com> X-IsSubscribed: yes Replace all custom "library" calls with compiler known patterns. gcc/ xxxx-xx-xx Claudiu Zissulescu * config/arc/arc.md (mulsi3): Remove call to mulsi_600_lib. (mulsi3_600_lib): Remove pattern. (umulsi3_highpart_600_lib_le): Likewise. (umulsi3_highpart): Remove call to umulsi3_highpart_600_lib_le. (umulsidi3): Remove call to umulsidi3_600_lib. (umulsidi3_600_lib): Remove pattern. (peephole2): Remove peephole using the above deprecated patterns. testsuite/ xxxx-xx-xx Claudiu Zissulescu * gcc.target/arc/mulsi3_highpart-2.c: Update test. libgcc/ xxxx-xx-xx Claudiu Zissulescu * config/arc/lib1funcs.S (_muldi3): New function. * config/arc/t-arc (LIB1ASMFUNCS): Add _muldi3. --- gcc/config/arc/arc.md | 158 ++---------------- .../gcc.target/arc/mulsi3_highpart-2.c | 5 +- libgcc/config/arc/lib1funcs.S | 54 ++++++ libgcc/config/arc/t-arc | 2 +- 4 files changed, 67 insertions(+), 152 deletions(-) diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 42ca820b91d..d73289a20c4 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -2076,44 +2076,21 @@ archs4x, archs4xd, archs4xd_slow" ;; SI <- SI * SI (define_expand "mulsi3" - [(set (match_operand:SI 0 "nonimmediate_operand" "") + [(set (match_operand:SI 0 "register_operand" "") (mult:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "nonmemory_operand" "")))] - "" + "TARGET_ANY_MPY" { - if (TARGET_MPY) - { - if (!register_operand (operands[0], SImode)) - { - rtx result = gen_reg_rtx (SImode); - - emit_insn (gen_mulsi3 (result, operands[1], operands[2])); - emit_move_insn (operands[0], result); - DONE; - } - } - else if (TARGET_MUL64_SET) + if (TARGET_MUL64_SET) { - rtx tmp = gen_reg_rtx (SImode); - emit_insn (gen_mulsi64 (tmp, operands[1], operands[2])); - emit_move_insn (operands[0], tmp); + emit_insn (gen_mulsi64 (operands[0], operands[1], operands[2])); DONE; } else if (TARGET_MULMAC_32BY16_SET) { - rtx tmp = gen_reg_rtx (SImode); - emit_insn (gen_mulsi32x16 (tmp, operands[1], operands[2])); - emit_move_insn (operands[0], tmp); + emit_insn (gen_mulsi32x16 (operands[0], operands[1], operands[2])); DONE; } - else - { - emit_move_insn (gen_rtx_REG (SImode, R0_REG), operands[1]); - emit_move_insn (gen_rtx_REG (SImode, R1_REG), operands[2]); - emit_insn (gen_mulsi3_600_lib ()); - emit_move_insn (operands[0], gen_rtx_REG (SImode, R0_REG)); - DONE; - } }) (define_insn_and_split "mulsi32x16" @@ -2229,27 +2206,6 @@ archs4x, archs4xd, archs4xd_slow" (set_attr "predicable" "yes,yes,no,yes") (set_attr "cond" "canuse,canuse,canuse_limm,canuse")]) -; If we compile without an mul option enabled, but link with libraries -; for a mul option, we'll see clobbers of multiplier output registers. -; There is also an implementation using norm that clobbers the loop registers. -(define_insn "mulsi3_600_lib" - [(set (reg:SI R0_REG) - (mult:SI (reg:SI R0_REG) (reg:SI R1_REG))) - (clobber (reg:SI RETURN_ADDR_REGNUM)) - (clobber (reg:SI R1_REG)) - (clobber (reg:SI R2_REG)) - (clobber (reg:SI R3_REG)) - (clobber (reg:DI MUL64_OUT_REG)) - (clobber (reg:SI LP_COUNT)) - (clobber (reg:SI LP_START)) - (clobber (reg:SI LP_END)) - (clobber (reg:CC CC_REG))] - "!TARGET_ANY_MPY - && SFUNC_CHECK_PREDICABLE" - "*return arc_output_libcall (\"__mulsi3\");" - [(set_attr "is_sfunc" "yes") - (set_attr "predicable" "yes")]) - (define_insn_and_split "mulsidi_600" [(set (match_operand:DI 0 "register_operand" "=c, c,c, c") (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%Rcq#q, c,c, c")) @@ -2504,48 +2460,6 @@ archs4x, archs4xd, archs4xd_slow" (set_attr "predicable" "yes,no,yes,no") (set_attr "cond" "canuse,nocond,canuse,nocond")]) -; Implementations include additional labels for umulsidi3, so we got all -; the same clobbers - plus one for the result low part. */ -(define_insn "umulsi3_highpart_600_lib_le" - [(set (reg:SI R1_REG) - (truncate:SI - (lshiftrt:DI - (mult:DI (zero_extend:DI (reg:SI R0_REG)) - (zero_extend:DI (reg:SI R1_REG))) - (const_int 32)))) - (clobber (reg:SI RETURN_ADDR_REGNUM)) - (clobber (reg:SI R0_REG)) - (clobber (reg:DI R2_REG)) - (clobber (reg:SI R12_REG)) - (clobber (reg:DI MUL64_OUT_REG)) - (clobber (reg:CC CC_REG))] - "!TARGET_BIG_ENDIAN - && !TARGET_ANY_MPY - && SFUNC_CHECK_PREDICABLE" - "*return arc_output_libcall (\"__umulsi3_highpart\");" - [(set_attr "is_sfunc" "yes") - (set_attr "predicable" "yes")]) - -(define_insn "umulsi3_highpart_600_lib_be" - [(set (reg:SI R0_REG) - (truncate:SI - (lshiftrt:DI - (mult:DI (zero_extend:DI (reg:SI R0_REG)) - (zero_extend:DI (reg:SI R1_REG))) - (const_int 32)))) - (clobber (reg:SI RETURN_ADDR_REGNUM)) - (clobber (reg:SI R1_REG)) - (clobber (reg:DI R2_REG)) - (clobber (reg:SI R12_REG)) - (clobber (reg:DI MUL64_OUT_REG)) - (clobber (reg:CC CC_REG))] - "TARGET_BIG_ENDIAN - && !TARGET_ANY_MPY - && SFUNC_CHECK_PREDICABLE" - "*return arc_output_libcall (\"__umulsi3_highpart\");" - [(set_attr "is_sfunc" "yes") - (set_attr "predicable" "yes")]) - ;; (zero_extend:DI (const_int)) leads to internal errors in combine, so we ;; need a separate pattern for immediates ;; ??? This is fine for combine, but not for reload. @@ -2572,23 +2486,11 @@ archs4x, archs4xd, archs4xd_slow" (zero_extend:DI (match_operand:SI 1 "register_operand" "")) (zero_extend:DI (match_operand:SI 2 "nonmemory_operand" ""))) (const_int 32))))] - "!TARGET_MUL64_SET && !TARGET_MULMAC_32BY16_SET" + "TARGET_MPY" " { rtx target = operands[0]; - if (!TARGET_MPY) - { - emit_move_insn (gen_rtx_REG (SImode, 0), operands[1]); - emit_move_insn (gen_rtx_REG (SImode, 1), operands[2]); - if (TARGET_BIG_ENDIAN) - emit_insn (gen_umulsi3_highpart_600_lib_be ()); - else - emit_insn (gen_umulsi3_highpart_600_lib_le ()); - emit_move_insn (target, gen_rtx_REG (SImode, 0)); - DONE; - } - if (!register_operand (target, SImode)) target = gen_reg_rtx (SImode); @@ -2607,7 +2509,7 @@ archs4x, archs4xd, archs4xd_slow" [(set (match_operand:DI 0 "register_operand" "") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) (zero_extend:DI (match_operand:SI 2 "nonmemory_operand" ""))))] - "" + "TARGET_ANY_MPY" { if (TARGET_PLUS_MACD) { @@ -2646,12 +2548,8 @@ archs4x, archs4xd, archs4xd_slow" DONE; } else - { - emit_move_insn (gen_rtx_REG (SImode, R0_REG), operands[1]); - emit_move_insn (gen_rtx_REG (SImode, R1_REG), operands[2]); - emit_insn (gen_umulsidi3_600_lib ()); - emit_move_insn (operands[0], gen_rtx_REG (DImode, R0_REG)); - DONE; + { + gcc_unreachable (); } }) @@ -2729,7 +2627,7 @@ archs4x, archs4xd, archs4xd_slow" (zero_extend:DI (match_operand:SI 2 "extend_operand" "cL"))))] "TARGET_MPY && !TARGET_PLUS_MACD" "#" - "reload_completed" + "TARGET_MPY && !TARGET_PLUS_MACD && reload_completed" [(const_int 0)] { int hi = !TARGET_BIG_ENDIAN; @@ -2743,42 +2641,6 @@ archs4x, archs4xd, archs4xd_slow" [(set_attr "type" "umulti") (set_attr "length" "8")]) -(define_insn "umulsidi3_600_lib" - [(set (reg:DI R0_REG) - (mult:DI (zero_extend:DI (reg:SI R0_REG)) - (zero_extend:DI (reg:SI R1_REG)))) - (clobber (reg:SI RETURN_ADDR_REGNUM)) - (clobber (reg:DI R2_REG)) - (clobber (reg:SI R12_REG)) - (clobber (reg:DI MUL64_OUT_REG)) - (clobber (reg:CC CC_REG))] - "!TARGET_ANY_MPY - && SFUNC_CHECK_PREDICABLE" - "*return arc_output_libcall (\"__umulsidi3\");" - [(set_attr "is_sfunc" "yes") - (set_attr "predicable" "yes")]) - -(define_peephole2 - [(parallel - [(set (reg:DI R0_REG) - (mult:DI (zero_extend:DI (reg:SI R0_REG)) - (zero_extend:DI (reg:SI R1_REG)))) - (clobber (reg:SI RETURN_ADDR_REGNUM)) - (clobber (reg:DI R2_REG)) - (clobber (reg:SI R12_REG)) - (clobber (reg:DI MUL64_OUT_REG)) - (clobber (reg:CC CC_REG))])] - "!TARGET_ANY_MPY - && peep2_regno_dead_p (1, TARGET_BIG_ENDIAN ? R1_REG : R0_REG)" - [(pc)] -{ - if (TARGET_BIG_ENDIAN) - emit_insn (gen_umulsi3_highpart_600_lib_be ()); - else - emit_insn (gen_umulsi3_highpart_600_lib_le ()); - DONE; -}) - (define_expand "addsi3" [(set (match_operand:SI 0 "dest_reg_operand" "") (plus:SI (match_operand:SI 1 "register_operand" "") diff --git a/gcc/testsuite/gcc.target/arc/mulsi3_highpart-2.c b/gcc/testsuite/gcc.target/arc/mulsi3_highpart-2.c index 4b54cbf6a52..22b28cf2507 100644 --- a/gcc/testsuite/gcc.target/arc/mulsi3_highpart-2.c +++ b/gcc/testsuite/gcc.target/arc/mulsi3_highpart-2.c @@ -1,7 +1,7 @@ /* { dg-do run } */ /* { dg-skip-if "ARC700 always has mpy option on" { arc700 } } */ /* { dg-skip-if "ARC600 doesn't have mpy instruction" { arc6xx } } */ -/* { dg-options "-O2 -mmpy-option=0 -w" } */ +/* { dg-options "-O2 -mmpy-option=0 -w -save-temps" } */ #include @@ -28,5 +28,4 @@ main (void) } /* { dg-final { scan-assembler-not "mpyhu\[ \t\]" } } */ -/* { dg-final { scan-assembler-not "@__muldi3" } } */ -/* { dg-final { scan-assembler "@__umulsi3_highpart" } } */ +/* { dg-final { scan-assembler "@__muldi3" } } */ diff --git a/libgcc/config/arc/lib1funcs.S b/libgcc/config/arc/lib1funcs.S index 9a626022612..249dd7a7ff7 100644 --- a/libgcc/config/arc/lib1funcs.S +++ b/libgcc/config/arc/lib1funcs.S @@ -232,6 +232,60 @@ SYM(__umulsi3_highpart): #endif #endif /* L_umulsidi3 */ +#ifdef L_muldi3 + .section .text + .align 4 + .global SYM(__muldi3) +SYM(__muldi3): +#ifdef __LITTLE_ENDIAN__ + push_s blink + mov_s r4,r3 ;4 + mov_s r5,r2 ;4 + mov_s r9,r0 ;4 + mov_s r8,r1 ;4 + bl.d @__umulsidi3 + mov_s r1,r2 ;4 + mov_s r6,r0 ;4 + mov_s r7,r1 ;4 + mov_s r0,r9 ;4 + bl.d @__mulsi3 + mov_s r1,r4 ;4 + mov_s r4,r0 ;4 + mov_s r1,r8 ;4 + bl.d @__mulsi3 + mov_s r0,r5 ;4 + pop_s blink + add_s r0,r0,r4 ;2 + add r1,r0,r7 + j_s.d [blink] + mov_s r0,r6 ;4 +#else + push_s blink + mov_s r5,r3 + mov_s r9,r2 + mov_s r4,r1 + mov_s r8,r0 + mov_s r0,r1 + bl.d @__umulsidi3 + mov_s r1,r3 + mov_s r7,r0 + mov_s r6,r1 + mov_s r0,r4 + bl.d @__mulsi3 + mov_s r1,r9 + mov_s r4,r0 + mov_s r1,r8 + bl.d @__mulsi3 + mov_s r0,r5 + pop_s blink + add_s r0,r0,r4 + add_s r0,r0,r7 + j_s.d [blink] + mov_s r1,r6 +#endif /* __LITTLE_ENDIAN__ */ +ENDFUNC(__muldi3) +#endif /* L_muldi3 */ + #ifdef L_umulsi3_highpart #include "ieee-754/arc-ieee-754.h" /* For use without a barrel shifter, and for ARC700 / ARC_MUL64, the diff --git a/libgcc/config/arc/t-arc b/libgcc/config/arc/t-arc index ad30fdb1db7..c79bc1cfdc4 100644 --- a/libgcc/config/arc/t-arc +++ b/libgcc/config/arc/t-arc @@ -21,7 +21,7 @@ CROSS_LIBGCC1 = libgcc1-asm.a LIB1ASMSRC = arc/lib1funcs.S -LIB1ASMFUNCS = _mulsi3 _umulsidi3 _umulsi3_highpart \ +LIB1ASMFUNCS = _mulsi3 _umulsidi3 _umulsi3_highpart _muldi3 \ _udivsi3 _divsi3 _umodsi3 _modsi3 \ _divmod_tools _clzsi2 \ _millicodethunk_st _millicodethunk_ld _millicodethunk_ret \