From patchwork Wed Oct 3 19:10:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 978495 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-486903-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="iEKWmaN0"; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="hJRm8VU9"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42QQZm5KhRz9s5c for ; Thu, 4 Oct 2018 05:10:21 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=TyHXGovznxIu RfMlI1/kHnmVgcV9et9LOkxEgxXihi3sfqjsRIqGhNQzMQYoTa64tGZwrNShxStN vaHAVXaNOm5HCsHaPtlWaPv/MlS0i145b6jAlkjR6O/kEK8Cotou1f9nxZsUWwmp pzLRWAU3zUx0sjv2aHGcdOu1eArSxKM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=pQv46r1FgHI8RWCmCT YnDu9mRPQ=; b=iEKWmaN0XUav8zSohP9yMhki3NzyCDektznshY+w/PMwcAJIbv TX1Qa2IKpSiTeGocXNQ9hNYqBcKj+f1ARCNmPMldLvFUDDl9GrzhGl+eerKb7Df9 3/NcSsXVcTva4OmhLyV3sFMiMMjzon6iIzi38F8IAjMqLVJhDvMIf3Lbg= Received: (qmail 14054 invoked by alias); 3 Oct 2018 19:10:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 14040 invoked by uid 89); 3 Oct 2018 19:10:14 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=Hx-spam-relays-external:209.85.210.195, H*RU:209.85.210.195, H*r:sk:x17-v6s, mabi X-HELO: mail-pf1-f195.google.com Received: from mail-pf1-f195.google.com (HELO mail-pf1-f195.google.com) (209.85.210.195) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 03 Oct 2018 19:10:12 +0000 Received: by mail-pf1-f195.google.com with SMTP id x17-v6so2135189pfh.5 for ; Wed, 03 Oct 2018 12:10:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id; bh=Laue4DvNd4n/p3FJGR4MSXH6nDDvNz2qwo9aNXeWk/s=; b=hJRm8VU90uPYOHVChOC9AJ5pXpnRXsqQwB5hBQvkbia2HIsWSlLkeGxMWXC+MAXRtf 7MQjDgWA/FP2EgyIMmaQnW2I2b7udc9KzCOjpd5fCUv1looKSIhOWG3xV2d/kNkViWXA 5M0HHUlcynhvyZ6F/grhwd6dzJ18nSJChqPNT+jT8iYtZeo/eb2ZCH8nHffU+EJs449v jMhhJQfgcg9IK2ZxrDdteD789w5gOri5R6Rw0on4VxfYfD04dnU0RpA6ymltFWbleWNT fExb2zDXKmbKhFITCqNaPX0jqKcumhhKFDhwBQ6hSjoBpdrzgmlX7aR97zSEcUhW3wNP /PtQ== Received: from rohan.guest.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id c21-v6sm3838378pfe.93.2018.10.03.12.10.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Oct 2018 12:10:10 -0700 (PDT) From: Jim Wilson To: gcc-patches@gcc.gnu.org Cc: Jim Wilson Subject: [PATCH] RISC-V: Add macro for ilp32e ABI. Cleanup white space. Date: Wed, 3 Oct 2018 12:10:07 -0700 Message-Id: <20181003191007.18274-1-jimw@sifive.com> Now that we officially allow -mabi=ilp32e to be used separately from the -march=rv32e option, we need a predefined macro for it so user code can detect the ABI. This patches adds a __riscv_abi_rve macro for that purpose. While writing this, I noticed some trailing white space in the file, and fixed that too. This was tested with riscv{32,64}-{elf,linux} cross builds. Also, hand testing to verify that the new macros is defined only when it should be defined. Committed. Jim gcc/ * config/riscv/riscv-c.c (riscv_cpu_cpp_builtins): For ABI_ILP32E, also define __riscv_abi_rve. Delete trailing white space. --- gcc/config/riscv/riscv-c.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/gcc/config/riscv/riscv-c.c b/gcc/config/riscv/riscv-c.c index 513f974d9aa..d3ecd0796e8 100644 --- a/gcc/config/riscv/riscv-c.c +++ b/gcc/config/riscv/riscv-c.c @@ -35,62 +35,65 @@ void riscv_cpu_cpp_builtins (cpp_reader *pfile) { builtin_define ("__riscv"); - + if (TARGET_RVC) builtin_define ("__riscv_compressed"); - + if (TARGET_RVE) builtin_define ("__riscv_32e"); if (TARGET_ATOMIC) builtin_define ("__riscv_atomic"); - + if (TARGET_MUL) builtin_define ("__riscv_mul"); if (TARGET_DIV) builtin_define ("__riscv_div"); if (TARGET_DIV && TARGET_MUL) builtin_define ("__riscv_muldiv"); - + builtin_define_with_int_value ("__riscv_xlen", UNITS_PER_WORD * 8); if (TARGET_HARD_FLOAT) builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8); - + if (TARGET_HARD_FLOAT && TARGET_FDIV) { builtin_define ("__riscv_fdiv"); builtin_define ("__riscv_fsqrt"); } - + switch (riscv_abi) { - case ABI_ILP32: case ABI_ILP32E: + builtin_define ("__riscv_abi_rve"); + gcc_fallthrough (); + + case ABI_ILP32: case ABI_LP64: builtin_define ("__riscv_float_abi_soft"); break; - + case ABI_ILP32F: case ABI_LP64F: builtin_define ("__riscv_float_abi_single"); break; - + case ABI_ILP32D: case ABI_LP64D: builtin_define ("__riscv_float_abi_double"); break; } - + switch (riscv_cmodel) { case CM_MEDLOW: builtin_define ("__riscv_cmodel_medlow"); break; - + case CM_MEDANY: builtin_define ("__riscv_cmodel_medany"); break; - + case CM_PIC: builtin_define ("__riscv_cmodel_pic"); break;