From patchwork Mon Sep 17 12:50:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu X-Patchwork-Id: 970586 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-485767-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="QLGWL4jt"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Ed44DSAk"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42DQwf3zCHz9sB5 for ; Mon, 17 Sep 2018 22:51:14 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=xqi5nIKg5nZOB8p6V7Hhv+yiW4SR2Vj4coDHmWmSj3WCIib+l2JVB 6oJb99O0NjpwkZ+msWl7lscI591ueJt0ukRVKJF8e23HEh2efIZAcwC11q4xBi12 YMj3jBqavakiN6sN9q91eKs53Ekn5PyslnCixj31H4orJQQDOk/JgY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=1YtIycPoypF09nMMspK3fbTyJjc=; b=QLGWL4jtulKjTdoS/m3Q JB1RUEm34A5EcjZSs5RESCi4kr4lI/8Gu68laKtQSqRExWm9uIQYlQI4VxOTnm5c owk/lVOE5tt/v3iHuAk7EYyVet60HpQ8zPMKmJcoU1sbdtUegiu7r8W7W69my9pa GyYG7FgncFV/VolOBqTDkz8= Received: (qmail 2397 invoked by alias); 17 Sep 2018 12:50:46 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 2284 invoked by uid 89); 17 Sep 2018 12:50:45 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.1 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=nb, NB, satisfy, sk:immedia X-HELO: mail-ed1-f67.google.com Received: from mail-ed1-f67.google.com (HELO mail-ed1-f67.google.com) (209.85.208.67) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 17 Sep 2018 12:50:43 +0000 Received: by mail-ed1-f67.google.com with SMTP id z27-v6so12779033edb.10 for ; Mon, 17 Sep 2018 05:50:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iUR+MfwonnxgERB3wJiOfKYgn2/Xto+zcRWS4X+HigM=; b=Ed44DSAkz7zhKniiFw8q7QmlDFEoDcwnOYQv4sUXlQPh7Xpv7tzMKO1/s9cuFWsfrJ 75rW6rfsIb1qvG/2MU4aDC27WPHSBaqRQNe3+aRRNOeo+8wa2L5bwsOInI48+nQ53oSg bUjMrECukZ5UrWujntu/yGWZaacu8qBQjXMxC+AhDWmD8IcwuP2cEWoc+fhQ3uFVgHIZ lSkKU0p0o/Imm3u8aQMlgDr/rkXzkqGYbp4iYCZRwZmFt+g8oDIXsJmgNQYLVTX0xm9j ReFNFypyFJYSKI1NIFiQGrk1X9nGjGOaY6NP7JHHHPSZhm+U6kG/cJtu4Tmx8ecqSlWE xeOA== Received: from localhost.localdomain ([188.241.79.25]) by smtp.gmail.com with ESMTPSA id z56-v6sm13395078edz.54.2018.09.17.05.50.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 17 Sep 2018 05:50:40 -0700 (PDT) From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Cc: fbedard@synopsys.com, andrew.burgess@embecosm.com Subject: [PATCH 2/2] [ARC] Avoid specific constants to end in limm field. Date: Mon, 17 Sep 2018 15:50:27 +0300 Message-Id: <20180917125027.10946-3-claziss@gmail.com> In-Reply-To: <20180917125027.10946-1-claziss@gmail.com> References: <20180917125027.10946-1-claziss@gmail.com> X-IsSubscribed: yes The 3-operand instructions accepts to place an immediate into the second operand. However, this immediate will end up in the long immediate field. This patch avoids constants to end up in the limm field for particular instructions when compiling for size. gcc/ xxxx-xx-xx Claudiu Zissulescu * config/arc/arc.md (*add_n): Clean up pattern, update instruction constraints. (ashlsi3_insn): Update instruction constraints. (ashrsi3_insn): Likewise. (rotrsi3): Likewise. (add_shift): Likewise. * config/arc/constraints.md (Csz): New 32 bit constraint. It avoids placing in the limm field small constants which, otherwise, could end into a small instruction. --- gcc/config/arc/arc.md | 51 +++++++++--------------- gcc/config/arc/constraints.md | 6 +++ gcc/testsuite/gcc.target/arc/tph_addx.c | 53 +++++++++++++++++++++++++ 3 files changed, 78 insertions(+), 32 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arc/tph_addx.c diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 2d108ef166d..c28a87cd3b0 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -3056,30 +3056,17 @@ core_3, archs4x, archs4xd, archs4xd_slow" (set (match_dup 3) (match_dup 4))]) (define_insn "*add_n" - [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcw,W,W,w,w") - (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "Rcqq,c,c,c,c,c") - (match_operand:SI 2 "_1_2_3_operand" "")) - (match_operand:SI 3 "nonmemory_operand" "0,0,c,?Cal,?c,??Cal")))] + [(set (match_operand:SI 0 "dest_reg_operand" "=q,r,r") + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "q,r,r") + (match_operand:SI 2 "_2_4_8_operand" "")) + (match_operand:SI 3 "nonmemory_operand" "0,r,Csz")))] "" - "add%c2%? %0,%3,%1%&" + "add%z2%?\\t%0,%3,%1%&" [(set_attr "type" "shift") - (set_attr "length" "*,4,4,8,4,8") - (set_attr "predicable" "yes,yes,no,no,no,no") - (set_attr "cond" "canuse,canuse,nocond,nocond,nocond,nocond") - (set_attr "iscompact" "maybe,false,false,false,false,false")]) - -(define_insn "*add_n" - [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcw,W, W,w,w") - (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "Rcqq, c,c, c,c,c") - (match_operand:SI 2 "_2_4_8_operand" "")) - (match_operand:SI 3 "nonmemory_operand" "0, 0,c,Cal,c,Cal")))] - "" - "add%z2%? %0,%3,%1%&" - [(set_attr "type" "shift") - (set_attr "length" "*,4,4,8,4,8") - (set_attr "predicable" "yes,yes,no,no,no,no") - (set_attr "cond" "canuse,canuse,nocond,nocond,nocond,nocond") - (set_attr "iscompact" "maybe,false,false,false,false,false")]) + (set_attr "length" "*,4,8") + (set_attr "predicable" "yes,no,no") + (set_attr "cond" "canuse,nocond,nocond") + (set_attr "iscompact" "maybe,false,false")]) ;; N.B. sub[123] has the operands of the MINUS in the opposite order from ;; what synth_mult likes. @@ -3496,7 +3483,7 @@ core_3, archs4x, archs4xd, archs4xd_slow" ; provide one alternatice for this, without condexec support. (define_insn "*ashlsi3_insn" [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,Rcqq,Rcqq,Rcw, w, w") - (ashift:SI (match_operand:SI 1 "nonmemory_operand" "!0,Rcqq, 0, 0, c,cCal") + (ashift:SI (match_operand:SI 1 "nonmemory_operand" "!0,Rcqq, 0, 0, c,cCsz") (match_operand:SI 2 "nonmemory_operand" "K, K,RcqqM, cL,cL,cCal")))] "TARGET_BARREL_SHIFTER && (register_operand (operands[1], SImode) @@ -3509,7 +3496,7 @@ core_3, archs4x, archs4xd, archs4xd_slow" (define_insn "*ashrsi3_insn" [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,Rcqq,Rcqq,Rcw, w, w") - (ashiftrt:SI (match_operand:SI 1 "nonmemory_operand" "!0,Rcqq, 0, 0, c,cCal") + (ashiftrt:SI (match_operand:SI 1 "nonmemory_operand" "!0,Rcqq, 0, 0, c,cCsz") (match_operand:SI 2 "nonmemory_operand" "K, K,RcqqM, cL,cL,cCal")))] "TARGET_BARREL_SHIFTER && (register_operand (operands[1], SImode) @@ -3536,7 +3523,7 @@ core_3, archs4x, archs4xd, archs4xd_slow" (define_insn "rotrsi3" [(set (match_operand:SI 0 "dest_reg_operand" "=Rcw, w, w") - (rotatert:SI (match_operand:SI 1 "register_operand" " 0,cL,cCal") + (rotatert:SI (match_operand:SI 1 "register_operand" " 0,cL,cCsz") (match_operand:SI 2 "nonmemory_operand" "cL,cL,cCal")))] "TARGET_BARREL_SHIFTER" "ror%? %0,%1,%2" @@ -4284,16 +4271,16 @@ core_3, archs4x, archs4xd, archs4xd_slow" (define_peephole2 [(set (match_operand:SI 0 "dest_reg_operand" "") (ashift:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "const_int_operand" ""))) + (match_operand:SI 2 "_1_2_3_operand" ""))) (set (match_operand:SI 3 "dest_reg_operand" "") (plus:SI (match_operand:SI 4 "nonmemory_operand" "") (match_operand:SI 5 "nonmemory_operand" "")))] - "(INTVAL (operands[2]) == 1 - || INTVAL (operands[2]) == 2 - || INTVAL (operands[2]) == 3) - && (true_regnum (operands[4]) == true_regnum (operands[0]) + "(true_regnum (operands[4]) == true_regnum (operands[0]) || true_regnum (operands[5]) == true_regnum (operands[0])) - && (peep2_reg_dead_p (2, operands[0]) || (true_regnum (operands[3]) == true_regnum (operands[0])))" + && (peep2_reg_dead_p (2, operands[0]) + || (true_regnum (operands[3]) == true_regnum (operands[0]))) + && !(optimize_size && satisfies_constraint_I (operands[4])) + && !(optimize_size && satisfies_constraint_I (operands[5]))" ;; the preparation statements take care to put proper operand in operands[4] ;; operands[4] will always contain the correct operand. This is added to satisfy commutativity [(set (match_dup 3) @@ -6329,7 +6316,7 @@ core_3, archs4x, archs4xd, archs4xd_slow" [(set (match_operand:SI 0 "register_operand" "=q,r,r") (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "q,r,r") (match_operand:SI 2 "_1_2_3_operand" "")) - (match_operand:SI 3 "nonmemory_operand" "0,r,Cal")))] + (match_operand:SI 3 "nonmemory_operand" "0,r,Csz")))] "" "add%2%?\\t%0,%3,%1" [(set_attr "length" "*,4,8") diff --git a/gcc/config/arc/constraints.md b/gcc/config/arc/constraints.md index f9ef3f94dfe..abfeedffe9a 100644 --- a/gcc/config/arc/constraints.md +++ b/gcc/config/arc/constraints.md @@ -428,6 +428,12 @@ && !arc_legitimate_pic_addr_p (op) && !satisfies_constraint_I (op)")) +(define_constraint "Csz" + "a 32 bit constant avoided when compiling for size." + (match_test "immediate_operand (op, VOIDmode) + && !arc_legitimate_pic_addr_p (op) + && !(satisfies_constraint_I (op) && optimize_size)")) + ; Note that the 'cryptic' register constraints will not make reload use the ; associated class to reload into, but this will not penalize reloading of any ; other operands, or using an alternate part of the same alternative. diff --git a/gcc/testsuite/gcc.target/arc/tph_addx.c b/gcc/testsuite/gcc.target/arc/tph_addx.c new file mode 100644 index 00000000000..f942ab19eb1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/tph_addx.c @@ -0,0 +1,53 @@ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ + +/* when compiling for size avoid the following peephole +------------------------------------------------------------- +Pattern 1 : r0 = r1 << {i} + r3 = r4/INT + r0 ;;and commutative + || + \/ + add{i} r3,r4/INT,r1 +------------------------------------------------------------- +*/ + +typedef int a; +typedef int b ; +struct c +{ + b d; +}; + +struct e +{ + a f; +}; + +int g(int family) +{ + switch (family) + case 2: + return sizeof(struct e); + return 0; +} + +int h(int family) +{ + return 1 + g(family) - 1 ; +} + +extern void m (void); + +int i(int j) +{ + struct c *hdr; + int k; + int l; + k = h(j); + l = sizeof(struct c) + k * 2; + hdr->d = l ; + if (j) + m(); +} + +/* { dg-final { scan-assembler-not "add\d" } } */