From patchwork Mon Jul 16 12:29:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu X-Patchwork-Id: 944366 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-481613-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="xxONS2yM"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="JIbLDEP4"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41TjS7480Fz9s29 for ; Mon, 16 Jul 2018 22:30:47 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=AwcX7JNMMNxHPx1Vc8xbOdQDptYEdUfTBOMfJ9AYC+C+ltLibF2zt eMqEMp2fZIaoO/fRf7U1F/ivFb9H7GWpxR1yumNWL3pNH+F9Hvo4tUVaUj/c5CBb GCfrKo620wvfpckCKsZ2lICCPK2rKLE+lLLth+yWJuWqq1nJ6OHuMU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=lGtZyO6gD7MZ2MgyZXRMOUyrmR4=; b=xxONS2yM+j0S9ZTe0Aeq fOLXyQpu8I7q+SjOO8Tr1fHqjYpCEE1FjWVjbhqAbtzKy4YEdOSlTK/Ab2tPX8zX g1bY/mzOvz9UZ/4MzNTGaClaUs5LwYUSXYaG5BguiU4xKFxsS3Xjn3UuQ14lQQ8X nKv/w+5AcAFUwhrfTZ+Mz4M= Received: (qmail 14123 invoked by alias); 16 Jul 2018 12:29:57 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 14021 invoked by uid 89); 16 Jul 2018 12:29:56 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=rf, Memory, Improve, multiplication X-HELO: mail-wr1-f50.google.com Received: from mail-wr1-f50.google.com (HELO mail-wr1-f50.google.com) (209.85.221.50) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 16 Jul 2018 12:29:54 +0000 Received: by mail-wr1-f50.google.com with SMTP id h10-v6so31719334wre.6 for ; Mon, 16 Jul 2018 05:29:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lsK3ZXtXh3XCdMttsyBExabylOnnQzVTemAh6gYRyCQ=; b=JIbLDEP4DPwthc9lo1hM7aqOONCaxhjWpIYGtYrGJZpcEBj6gEnPXPl46Y2NV2Qwjk a7iOzdiDEwxiuXKdnYBYOM1IbqJUf+hWdNyX1NRLP03HH9v5JrRwClmjwTiHWoJDFASm OhOMjQyCRNMGf76owcPuiCWw2md0yTklhjkSnNdNEnmkggLRwATOpTWkcEL0jSW0/Ncg Im1MNSv3OiSrjjYsItJVAJK+TkfP6Wk3CQ+6A5Hh+4o+WiO6qqWl0YPax72rY/FaNuf+ 9MxfbowshS9dLaJ49Y/IlBHWQ/OQ3KqrO/Zq0vFoIEvjN4o1kO0aynAB/riLo6EghZOD CroQ== Received: from localhost.localdomain ([188.241.79.25]) by smtp.gmail.com with ESMTPSA id 73-v6sm6135757wmo.21.2018.07.16.05.29.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Jul 2018 05:29:51 -0700 (PDT) From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Cc: fbedard@synopsys.com, andrew.burgess@embecosm.com Subject: [PATCH 3/4] [ARC] Improve instruction selection for fp moves. Date: Mon, 16 Jul 2018 15:29:44 +0300 Message-Id: <20180716122945.9375-3-claziss@gmail.com> In-Reply-To: <20180716122945.9375-1-claziss@gmail.com> References: <20180716122945.9375-1-claziss@gmail.com> X-IsSubscribed: yes Improve selection of short instruction for fp-moves. gcc/ 2018-05-17 Claudiu Zissulescu * config/arc/arc.md (movsf_insn): Add short instruction selection. * config/arc/constraints.md (CfZ): New constraint. * config/arc/fpu.md (addssf3_fpu): Use CfZ constraint. (subsf3_fpu): Likewise. (cmpsf_fpu): Likewise. (cmpsf_fpu_uneq): Likewise. --- gcc/config/arc/arc.md | 25 +++++++++------ gcc/config/arc/constraints.md | 6 ++++ gcc/config/arc/fpu.md | 59 +++++++++++++++++------------------ 3 files changed, 50 insertions(+), 40 deletions(-) diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 26aa3b31649..8f27c0f2c05 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -1294,19 +1294,24 @@ archs4x, archs4xd, archs4xd_slow" "if (prepare_move_operands (operands, SFmode)) DONE;") (define_insn "*movsf_insn" - [(set (match_operand:SF 0 "move_dest_operand" "=h,w,w,r,m") - (match_operand:SF 1 "move_src_operand" "hCm1,c,E,m,c"))] + [(set (match_operand:SF 0 "move_dest_operand" "=h,h, r,r, q,S,Usc,r,m") + (match_operand:SF 1 "move_src_operand" "hCfZ,E,rCfZ,E,Uts,q, E,m,r"))] "register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)" "@ - mov%? %0,%1 - mov%? %0,%1 - mov%? %0,%1 ; %A1 - ld%U1%V1 %0,%1 - st%U0%V0 %1,%0" - [(set_attr "type" "move,move,move,load,store") - (set_attr "predicable" "no,yes,yes,no,no") - (set_attr "iscompact" "true,false,false,false,false")]) + mov%?\\t%0,%1 + mov%?\\t%0,%1 ; %A1 + mov%?\\t%0,%1 + mov%?\\t%0,%1 ; %A1 + ld%?%U1\\t%0,%1 + st%?\\t%1,%0 + st%U0%V0\\t%1,%0 + ld%U1%V1\\t%0,%1 + st%U0%V0\\t%1,%0" + [(set_attr "type" "move,move,move,move,load,store,store,load,store") + (set_attr "predicable" "no,no,yes,yes,no,no,no,no,no") + (set_attr "length" "*,*,4,*,*,*,*,*,*") + (set_attr "iscompact" "true,true_limm,false,false,true,true,false,false,false")]) (define_expand "movdf" [(set (match_operand:DF 0 "move_dest_operand" "") diff --git a/gcc/config/arc/constraints.md b/gcc/config/arc/constraints.md index c304d535ad8..f9ef3f94dfe 100644 --- a/gcc/config/arc/constraints.md +++ b/gcc/config/arc/constraints.md @@ -314,6 +314,12 @@ (and (match_code "const_double") (match_test "1"))) +(define_constraint "CfZ" + "@internal + Match a floating-point zero" + (and (match_code "const_double") + (match_test "op == CONST0_RTX (SFmode)"))) + ;; Memory constraints (define_memory_constraint "T" "@internal diff --git a/gcc/config/arc/fpu.md b/gcc/config/arc/fpu.md index 9457922667e..6289e9c3f59 100644 --- a/gcc/config/arc/fpu.md +++ b/gcc/config/arc/fpu.md @@ -6,34 +6,34 @@ ;; Addition (define_insn "*addsf3_fpu" - [(set (match_operand:SF 0 "register_operand" "=r,r,r,r,r") - (plus:SF (match_operand:SF 1 "nonmemory_operand" "%0,r,0,r,F") - (match_operand:SF 2 "nonmemory_operand" "r,r,F,F,r")))] + [(set (match_operand:SF 0 "register_operand" "=r,r, r,r,r,r") + (plus:SF (match_operand:SF 1 "nonmemory_operand" "%0,r, r,0,r,F") + (match_operand:SF 2 "nonmemory_operand" "r,r,CfZ,F,F,r")))] "TARGET_FP_SP_BASE && (register_operand (operands[1], SFmode) || register_operand (operands[2], SFmode))" - "fsadd%? %0,%1,%2" - [(set_attr "length" "4,4,8,8,8") + "fsadd%?\\t%0,%1,%2" + [(set_attr "length" "4,4,4,8,8,8") (set_attr "iscompact" "false") (set_attr "type" "fpu") - (set_attr "predicable" "yes,no,yes,no,no") - (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond") + (set_attr "predicable" "yes,no,no,yes,no,no") + (set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond,nocond") ]) ;; Subtraction (define_insn "*subsf3_fpu" - [(set (match_operand:SF 0 "register_operand" "=r,r,r,r,r") - (minus:SF (match_operand:SF 1 "nonmemory_operand" "0,r,0,r,F") - (match_operand:SF 2 "nonmemory_operand" "r,r,F,F,r")))] + [(set (match_operand:SF 0 "register_operand" "=r,r, r,r,r,r") + (minus:SF (match_operand:SF 1 "nonmemory_operand" "0,r, r,0,r,F") + (match_operand:SF 2 "nonmemory_operand" "r,r,CfZ,F,F,r")))] "TARGET_FP_SP_BASE && (register_operand (operands[1], SFmode) || register_operand (operands[2], SFmode))" - "fssub%? %0,%1,%2" - [(set_attr "length" "4,4,8,8,8") + "fssub%?\\t%0,%1,%2" + [(set_attr "length" "4,4,4,8,8,8") (set_attr "iscompact" "false") (set_attr "type" "fpu") - (set_attr "predicable" "yes,no,yes,no,no") - (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond") + (set_attr "predicable" "yes,no,no,yes,no,no") + (set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond,nocond") ]) ;; Multiplication @@ -44,7 +44,7 @@ "TARGET_FP_SP_BASE && (register_operand (operands[1], SFmode) || register_operand (operands[2], SFmode))" - "fsmul%? %0,%1,%2" + "fsmul%?\\t%0,%1,%2" [(set_attr "length" "4,4,8,8,8") (set_attr "iscompact" "false") (set_attr "type" "fpu") @@ -108,7 +108,7 @@ "TARGET_FP_SP_FUSED && (register_operand (operands[1], SFmode) || register_operand (operands[2], SFmode))" - "fsmsub%? %0,%1,%2" + "fsmsub%?\\t%0,%1,%2" [(set_attr "length" "4,4,8,8,8") (set_attr "predicable" "yes,no,yes,no,no") (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond") @@ -178,7 +178,7 @@ (match_operand:DF 2 "even_register_operand" "r,r") (reg:DF ARCV2_ACC)))] "TARGET_FP_DP_FUSED" - "fdmadd%? %0,%1,%2" + "fdmadd%?\\t%0,%1,%2" [(set_attr "length" "4,4") (set_attr "predicable" "yes,no") (set_attr "cond" "canuse,nocond") @@ -191,7 +191,7 @@ (match_operand:DF 2 "even_register_operand" "r,r") (reg:DF ARCV2_ACC)))] "TARGET_FP_DP_FUSED" - "fdmsub%? %0,%1,%2" + "fdmsub%?\\t%0,%1,%2" [(set_attr "length" "4,4") (set_attr "predicable" "yes,no") (set_attr "cond" "canuse,nocond") @@ -206,7 +206,7 @@ "TARGET_FP_SP_SQRT && (register_operand (operands[1], SFmode) || register_operand (operands[2], SFmode))" - "fsdiv%? %0,%1,%2" + "fsdiv%?\\t%0,%1,%2" [(set_attr "length" "4,4,8,8,8") (set_attr "iscompact" "false") (set_attr "type" "fpu_sdiv") @@ -225,31 +225,31 @@ [(set (match_operand:SF 0 "register_operand" "=r,r") (sqrt:SF (match_operand:SF 1 "nonmemory_operand" "r,F")))] "TARGET_FP_SP_SQRT" - "fssqrt %0,%1" + "fssqrt\\t%0,%1" [(set_attr "length" "4,8") (set_attr "type" "fpu_sdiv")]) ;; Comparison (define_insn "*cmpsf_fpu" [(set (reg:CC_FPU CC_REG) - (compare:CC_FPU (match_operand:SF 0 "register_operand" "r,r") - (match_operand:SF 1 "nonmemory_operand" "r,F")))] + (compare:CC_FPU (match_operand:SF 0 "register_operand" "r, r,r") + (match_operand:SF 1 "nonmemory_operand" "r,CfZ,F")))] "TARGET_FP_SP_BASE" - "fscmp%? %0, %1" - [(set_attr "length" "4,8") + "fscmp%?\\t%0,%1" + [(set_attr "length" "4,4,8") (set_attr "iscompact" "false") (set_attr "cond" "set") (set_attr "type" "fpu") - (set_attr "predicable" "yes,yes")]) + (set_attr "predicable" "yes")]) (define_insn "*cmpsf_fpu_uneq" [(set (reg:CC_FPU_UNEQ CC_REG) (compare:CC_FPU_UNEQ - (match_operand:SF 0 "register_operand" "r,r") - (match_operand:SF 1 "nonmemory_operand" "r,F")))] + (match_operand:SF 0 "register_operand" "r, r,r") + (match_operand:SF 1 "nonmemory_operand" "r,CfZ,F")))] "TARGET_FP_SP_BASE" - "fscmp %0, %1\\n\\tmov.v.f 0,0\\t;set Z flag" - [(set_attr "length" "8,12") + "fscmp\\t%0,%1\\n\\tmov.v.f\\t0,0\\t;set Z flag" + [(set_attr "length" "8,8,12") (set_attr "iscompact" "false") (set_attr "cond" "set") (set_attr "type" "fpu")]) @@ -274,7 +274,6 @@ (set_attr "cond" "canuse,nocond") ]) - ;; Subtraction (define_insn "*subdf3_fpu" [(set (match_operand:DF 0 "even_register_operand" "=r,r")