From patchwork Thu Nov 30 21:52:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 843200 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-468282-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="xNDspCoy"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ynrk932j4z9sBZ for ; Fri, 1 Dec 2017 08:53:03 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:mime-version:content-type:message-id; q=dns; s= default; b=QbChnk1rrMqc0tn1aPijMuJXHbfBbidU489CxQv5TaKumjveuMgMy exsySWdsRv6NO9r9laMJR+j1b6vTmxGpFxTT+r6mE14hZUxPWKXir1Wj19c6aF6M vTSF0BOjtu4Z3mKsYw6/X+HKcw6OZWhWRLLsZc/5ohiztWSu0mdjMQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:mime-version:content-type:message-id; s= default; bh=0et25IMb/CnS1d9Zx4wXprrBe9Y=; b=xNDspCoyZ6S/ID7b0Ue3 hBKUCk+RH+4fMnaErdSEylNh2cbo6W2Wxaly9x9yICpQvx41FlEAtakGxTO4ziG1 uzH+QEffkazyQzDRtskjnN37fJCrTHMpyqOVhTWGDWkVv+1Q9S0/HpghHTcATjr5 kWUmcxh7ZJpXmJASsriYyP4= Received: (qmail 96537 invoked by alias); 30 Nov 2017 21:52:54 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 96524 invoked by uid 89); 30 Nov 2017 21:52:53 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-9.4 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, KAM_LAZY_DOMAIN_SECURITY, KAM_NUMSUBJECT, KAM_SHORT, KB_WAM_FROM_NAME_SINGLEWORD, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.2 spammy=enabler X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 30 Nov 2017 21:52:51 +0000 Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id vAULqg5M082671 for ; Thu, 30 Nov 2017 16:52:50 -0500 Received: from e17.ny.us.ibm.com (e17.ny.us.ibm.com [129.33.205.207]) by mx0a-001b2d01.pphosted.com with ESMTP id 2ejsmd2e81-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 30 Nov 2017 16:52:49 -0500 Received: from localhost by e17.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 30 Nov 2017 16:52:45 -0500 Received: from b01ledav005.gho.pok.ibm.com (b01ledav005.gho.pok.ibm.com [9.57.199.110]) by b01cxnp23034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id vAULqi9I46858452; Thu, 30 Nov 2017 21:52:44 GMT Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5850FAE043; Thu, 30 Nov 2017 16:53:41 -0500 (EST) Received: from ibm-tiger.the-meissners.org (unknown [9.32.77.111]) by b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP id 3DC60AE034; Thu, 30 Nov 2017 16:53:41 -0500 (EST) Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id 619CE47E6A; Thu, 30 Nov 2017 16:52:44 -0500 (EST) Date: Thu, 30 Nov 2017 16:52:44 -0500 From: Michael Meissner To: GCC Patches , Segher Boessenkool , David Edelsohn , Bill Schmidt Subject: [PATCH #2], PR target/81959, Fix ++int to _Float128 conversion on power9 Mail-Followup-To: Michael Meissner , GCC Patches , Segher Boessenkool , David Edelsohn , Bill Schmidt MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-GCONF: 00 x-cbid: 17113021-0040-0000-0000-000003CACD92 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00008130; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000242; SDB=6.00953560; UDB=6.00481822; IPR=6.00733635; BA=6.00005722; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00018278; XFM=3.00000015; UTC=2017-11-30 21:52:46 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17113021-0041-0000-0000-000007BFFD67 Message-Id: <20171130215244.GA21037@ibm-tiger.the-meissners.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-11-30_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1711300279 X-IsSubscribed: yes I submitted the original version of the patch back in August, and then I forgot about it. https://gcc.gnu.org/ml/gcc-patches/2017-08/msg01600.html Hi Mike, On Mon, Aug 28, 2017 at 02:50:02PM -0400, Michael Meissner wrote: > When I added the optimization for loading 32-bit values directly into the > vector registers from memory to convert to IEEE 128-bit floating point, I > forgot to make sure the address did not have PRE_INCREMENT, etc. addressing. > * config/rs6000/rs6000.md (float_si2_hw): If register > allocation hasn't been done, make sure the memory address is > X-FORM (register+register). > (floatuns_si2_hw2): Likewise. Why is it okay after RA but not before? Register allocation has fixed the address due to the 'Z' constraint, so it is no longer an AUTOINC address. I've fixed it so that the function rs6000_address_for_fpconvert checks whether it is being called after register allocation, and if so, it does nothing. > --- gcc/config/rs6000/rs6000.md (revision 251358) > +++ gcc/config/rs6000/rs6000.md (working copy) > @@ -14505,6 +14505,9 @@ (define_insn_and_split "float_si2_ > { > if (GET_CODE (operands[2]) == SCRATCH) > operands[2] = gen_reg_rtx (DImode); > + > + if (MEM_P (operands[1]) && !reload_completed) > + operands[1] = rs6000_address_for_fpconvert (operands[1]); > }) It will need a comment here, then (other callers of rs6000_address_for_fpconvert do not test for !reload_completed). All of the other uses of rs6000_address_for_fpconvert are either in define_expands or on the first splitter pass, which occurs before register allocation. Or maybe the predicate should be stricter in all these cases? nonimmediate_operand allows a lot ;-) No, then it tends to generate worse code if it is done before the first split pass (because it no longer keeps the address together). I've been thinking that in general, we should replace these calls with a new predicate that before register allocation allows normal memory addresses, but during/after RA, it becomes more strict. In my experience, with RELOAD that wasn't feasible, but LRA can handle it (and RELOAD is no longer an issue). > --- gcc/testsuite/gcc.target/powerpc/pr81959.c (revision 0) > +++ gcc/testsuite/gcc.target/powerpc/pr81959.c (revision 0) > @@ -0,0 +1,25 @@ > +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ > +/* { dg-require-effective-target powerpc_p9vector_ok } */ > +/* { dg-options "-mpower9-vector -O2 -mfloat128" } */ powerpc*-*-*, or does that not work? It needs 64-bit because various machine independent parts of the compiler want to use TImode if there is arithmetic support for KFmode to copy things, and TImode isn't supported in 32-bit. The __float128 support is not built if the compiler is a 32-bit compiler (the enabler for _float128 is in linux64.h) Here is the current version of the patch. I have done bootstraps and make check with no regressions. Can I check this into the trunk? The bug shows up in GCC 7 as well. Assuming it backports cleanly, can I check this into GCC 7 also? [gcc] 2017-11-30 Michael Meissner PR target/81959 * config/rs6000/rs6000.c (rs6000_address_for_fpconvert): Check for whether we can allocate pseudos before trying to fix an address. * config/rs6000/rs6000.md (float_si2_hw): Make sure the memory address is indexed or indirect. (floatuns_si2_hw2): Likewise. [gcct/testsuite] 2017-11-30 Michael Meissner PR target/81959 * gcc.target/powerpc/pr81959.c: New test. Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 255177) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -37897,7 +37897,8 @@ rs6000_address_for_fpconvert (rtx x) gcc_assert (MEM_P (x)); addr = XEXP (x, 0); - if (! legitimate_indirect_address_p (addr, reload_completed) + if (can_create_pseudo_p () + && ! legitimate_indirect_address_p (addr, reload_completed) && ! legitimate_indexed_address_p (addr, reload_completed)) { if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC) Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 255177) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -14636,6 +14636,9 @@ (define_insn_and_split "float_si2_ { if (GET_CODE (operands[2]) == SCRATCH) operands[2] = gen_reg_rtx (DImode); + + if (MEM_P (operands[1])) + operands[1] = rs6000_address_for_fpconvert (operands[1]); }) (define_insn_and_split "float2" @@ -14699,6 +14702,9 @@ (define_insn_and_split "floatuns_s { if (GET_CODE (operands[2]) == SCRATCH) operands[2] = gen_reg_rtx (DImode); + + if (MEM_P (operands[1])) + operands[1] = rs6000_address_for_fpconvert (operands[1]); }) (define_insn_and_split "floatuns2" Index: gcc/testsuite/gcc.target/powerpc/pr81959.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/pr81959.c (nonexistent) +++ gcc/testsuite/gcc.target/powerpc/pr81959.c (working copy) @@ -0,0 +1,25 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mpower9-vector -O2 -mfloat128" } */ + +/* PR 81959, the compiler raised on unrecognizable insn message in converting + int to __float128, where the int had a PRE_INC in the address. */ + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE 1024 +#endif + +void +convert_int_to_float128 (__float128 * __restrict__ p, + int * __restrict__ q) +{ + unsigned long i; + + for (i = 0; i < ARRAY_SIZE; i++) + p[i] = (__float128)q[i]; +} + +/* { dg-final { scan-assembler {\mlfiwax\M|\mlxsiwax\M} } } */ +/* { dg-final { scan-assembler {\mxscvsdqp\M} } } */ +/* { dg-final { scan-assembler-not {\mmtvsrd\M} } } */ +/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */