From patchwork Tue Nov 28 00:55:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 841919 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-468010-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="GJPxi9C2"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ym4wR538Rz9rvt for ; Tue, 28 Nov 2017 11:55:47 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=YjKZGeJjYbv7 PSueZ9bvBocEbyPqkWCQGC1/mh6gP2VakTXvrf38t6OKTnB8ZwQ2QgMWzlRrzdu+ DOOj1qYy3Ks4DyVyt6rHv+lgOfLhCBONR8ztX70yqiihF1p6R17aZHxMglVWcxpS AZ0rihT0ZzQNmJyC1R6FzniWJksAfFs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=zmcdeZ71U5sQnLza2F C9Ahnr4M0=; b=GJPxi9C2IPPd49P5wpxrS8p/l/HJRPtiVIlIR/OQzMai/yQb7c N0wHQRUxdzuECKfcwQzEAYBf3wEfRBEAC/41BejPR+5uiledoIY3kZ/4nGPUOZZ4 +DkIfsxQRPDP8MZQOBA9vnnfNKN6Ps+q2/h+nZdWNimfZvlGumI521WrU= Received: (qmail 30225 invoked by alias); 28 Nov 2017 00:55:37 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 30079 invoked by uid 89); 28 Nov 2017 00:55:36 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.6 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KB_WAM_FROM_NAME_SINGLEWORD, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=H*RU:209.85.160.65, Hx-spam-relays-external:209.85.160.65, spike X-HELO: mail-pl0-f65.google.com Received: from mail-pl0-f65.google.com (HELO mail-pl0-f65.google.com) (209.85.160.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 28 Nov 2017 00:55:34 +0000 Received: by mail-pl0-f65.google.com with SMTP id 61so9591318plf.4 for ; Mon, 27 Nov 2017 16:55:34 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=IA04jOdX9Jt8UO6RKCRGu3/7GBXzn9B3LBNsrof+KDU=; b=WnfWPI/FpV81X4a0z3A9RNsWRjEJfQ9lDRDuCRkzHLHp0o7sT2MIRy0pmMYaI7mLqq r49AN2PdZ3hKMn1RozArc/S9eJNQ8nr8wZqvn/6O7McC0oyXUQ1WDWW++k/454cfVlP+ kPvE9GR/zKtAmpy0DZqG12Sp1cz5JTrHJJg+9p1+MjQ0l7mSv9S3orlR9wDTk2EfWlKn 0pRYw6/JDWgxyBykUkwbOOUgh2Pt95ibQP/BeHsu5B67CLqS/JJ+Q2+s94Nbz0ixNQrG pQEIKeIhLPI2pn+yTn0XTtKvQU4qKl/SRljHQFdfFBPOhxyu/kWjYBTGzEr5H4HoZ/U6 4Lww== X-Gm-Message-State: AJaThX5FmsMSoAIHS7lyKk12X//UmGGdtByUa75hIMseIALCBe09Yi9s P28p06PJpXOzFy/j29gXfm8lAWtD/FA= X-Google-Smtp-Source: AGs4zMZFkn0NZSJ16maO/QYGKE65EUsG5D29nArIjQomnV72MY00FX0DJSs6q0BXBWVtYCz8FSJdUQ== X-Received: by 10.159.211.11 with SMTP id bc11mr40198837plb.187.1511830532606; Mon, 27 Nov 2017 16:55:32 -0800 (PST) Received: from rohan.internal.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id 76sm53214483pfn.179.2017.11.27.16.55.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 27 Nov 2017 16:55:32 -0800 (PST) From: Jim Wilson To: gcc-patches@gcc.gnu.org Cc: Jim Wilson Subject: [PATCH, gcc-7] Fix riscv linux kernel boot failure. Date: Mon, 27 Nov 2017 16:55:28 -0800 Message-Id: <20171128005528.24070-1-jimw@sifive.com> This patch is necessary in order to successfully boot a linux kernel on the UCB spike simulator. Riscv loads sign-extend by default, but this wasn't explicitly mentioned in the pic load patterns, resulting in some bad code generation. Fixed by adding an explicit sign_extend operation to the current pattern, and adding a second pattern for the zero_extend case. Tested with a linux kernel boot on spike, and a gcc testsuite run. There were no regressions. Committed. gcc/ Backport from mainline 2017-10-25 Palmer Dabbelt * config/riscv/riscv.md (ZERO_EXTEND_LOAD): Define. * config/riscv/pic.md (local_pic_load): Rename to local_pic_load_s, mark as a sign-extending load. (local_pic_load_u): Define. --- gcc/config/riscv/pic.md | 11 +++++++++-- gcc/config/riscv/riscv.md | 3 +++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/pic.md b/gcc/config/riscv/pic.md index 6a29ead..03b8f9b 100644 --- a/gcc/config/riscv/pic.md +++ b/gcc/config/riscv/pic.md @@ -22,13 +22,20 @@ ;; Simplify PIC loads to static variables. ;; These should go away once we figure out how to emit auipc discretely. -(define_insn "*local_pic_load" +(define_insn "*local_pic_load_s" [(set (match_operand:ANYI 0 "register_operand" "=r") - (mem:ANYI (match_operand 1 "absolute_symbolic_operand" "")))] + (sign_extend:ANYI (mem:ANYI (match_operand 1 "absolute_symbolic_operand" ""))))] "USE_LOAD_ADDRESS_MACRO (operands[1])" "\t%0,%1" [(set (attr "length") (const_int 8))]) +(define_insn "*local_pic_load_u" + [(set (match_operand:ZERO_EXTEND_LOAD 0 "register_operand" "=r") + (zero_extend:ZERO_EXTEND_LOAD (mem:ZERO_EXTEND_LOAD (match_operand 1 "absolute_symbolic_operand" ""))))] + "USE_LOAD_ADDRESS_MACRO (operands[1])" + "u\t%0,%1" + [(set (attr "length") (const_int 8))]) + (define_insn "*local_pic_load" [(set (match_operand:ANYF 0 "register_operand" "=f") (mem:ANYF (match_operand 1 "absolute_symbolic_operand" ""))) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 4cbb243..c478e03 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -259,6 +259,9 @@ ;; Iterator for QImode extension patterns. (define_mode_iterator SUPERQI [HI SI (DI "TARGET_64BIT")]) +;; Iterator for extending loads. +(define_mode_iterator ZERO_EXTEND_LOAD [QI HI (SI "TARGET_64BIT")]) + ;; Iterator for hardware integer modes narrower than XLEN. (define_mode_iterator SUBX [QI HI (SI "TARGET_64BIT")])