From patchwork Sat Nov 18 00:09:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 839186 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-467240-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="DYDVzyxu"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ydwNB08spz9s7C for ; Sat, 18 Nov 2017 11:09:57 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:date:message-id:cc:from:to; q=dns; s=default; b=U/6IJfB fhQwhoLkKplmEXWdt9Ep7TplDJ8JiKqdWuW2rC8GY3WgT30dn7fu3SQ1im2t4Q9w ga7kXySuA/rqi03RffHFC0/RU+QagGdzEf/0awafRYcEgu06+KuBJCwDPWGARJkl JnTIc8e7gIP4OLQ2nROrvDNSp1ClkuMpVg0g= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:date:message-id:cc:from:to; s=default; bh=0tXLmEb41UXZj SEAPYQMIBFLUkk=; b=DYDVzyxuZC8+/pVe32RcJC5iGIiKYe+oKO8P/lBdf9ODn Pkrj1fPaaT8r3HoFqwT5r746DT17mJlho0iCmH4UydvdfUvjB+4r2slEtGXYYQHo 3NeM38DVg2MndviWh0WVDWYrEu3bhTCokTqPBUneKc02sEkoKQwfyth7PQMjgc= Received: (qmail 63100 invoked by alias); 18 Nov 2017 00:09:49 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 63077 invoked by uid 89); 18 Nov 2017 00:09:48 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.2 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_NUMSUBJECT, KB_WAM_FROM_NAME_SINGLEWORD, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-pf0-f196.google.com Received: from mail-pf0-f196.google.com (HELO mail-pf0-f196.google.com) (209.85.192.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 18 Nov 2017 00:09:46 +0000 Received: by mail-pf0-f196.google.com with SMTP id 17so3044311pfn.12 for ; Fri, 17 Nov 2017 16:09:46 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:cc:from:to; bh=Xj0ZBLA9LMLaS6vuXzSIGXDkqM3dV0+FYWaXaG38uPA=; b=XxIrrRJNoWC0ELuZdTaYsQI+cXQOH61mr+5IlYeQWAkSWeARtj/wzCiE2IlUhHOeVu 4uXKB/sPUWA+CxIw+I2qQ8Io0bpdEr2liBqlxgIFQAP0cQwxMSU3aTolpRBX/WB2nBFU JIxXaW9goh/aEv7Vkd2/vNqlukpfkeT+uSu6G20H3kwzNS66VMQDWuzLg76hBW9z4CoC CaksjYw3vbXXlEknSkOmi2T1iO8NjF5G9YzlIrro1xfGsKVTRWfFW1+uUUBlulsao4Y1 +GsHRjdsYXenShQduanKvz8XQ6I2JqU+MQQHG02TvkRiqh3PaAFIlaceRiDLF5TXkYxp RKHQ== X-Gm-Message-State: AJaThX4ARf5op2QgxKrz5ejBqaKrIKCpsNUqTzyUOWE8lCe1TNphtdD1 zfpZbUzooZIzIwF9E8SlEces+A== X-Google-Smtp-Source: AGs4zMZMZBuY+VkQCCdMcIY/BTle22IvEWEaaagWqDM5dQsnL/8KVMaQjXli1EhXVCe0c1wcibxd4A== X-Received: by 10.84.164.231 with SMTP id l36mr6743447plg.179.1510963784942; Fri, 17 Nov 2017 16:09:44 -0800 (PST) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id r188sm9660502pfr.123.2017.11.17.16.09.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Nov 2017 16:09:44 -0800 (PST) Subject: [PATCH] RISC-V: Implement __umulsidi3, umul_ppmm and __muluw3 Date: Fri, 17 Nov 2017 16:09:23 -0800 Message-Id: <20171118000923.19152-1-palmer@dabbelt.com> Cc: patches@groups.riscv.org, Kito Cheng From: Palmer Dabbelt To: gcc-patches@gcc.gnu.org X-IsSubscribed: yes From: Kito Cheng 2017-11-17 Kito Cheng * longlong.h [__riscv] (__umulsidi3): Define. [__riscv] (umul_ppmm) Likewise. [__riscv] (__muluw3) Likewise. --- include/longlong.h | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/include/longlong.h b/include/longlong.h index c24568acea07..e61947d6c307 100644 --- a/include/longlong.h +++ b/include/longlong.h @@ -1050,6 +1050,56 @@ extern UDItype __umulsidi3 (USItype, USItype); } while (0) #endif +#if defined(__riscv) +#ifdef __riscv_mul +#define __umulsidi3(u,v) ((UDWtype)(UWtype)(u) * (UWtype)(v)) +#define __muluw3(a, b) ((UWtype)(a) * (UWtype)(b)) +#else +#if __riscv_xlen == 32 + #define MULUW3 "call __mulsi3" +#elif __riscv_xlen == 64 + #define MULUW3 "call __muldi3" +#else +#error unsupport xlen +#endif /* __riscv_xlen */ +/* We rely on the fact that MULUW3 doesn't clobber the t-registers. */ +#define __muluw3(a, b) \ + ({ \ + register UWtype __op0 asm ("a0") = a; \ + register UWtype __op1 asm ("a1") = b; \ + asm volatile (MULUW3 \ + : "+r" (__op0), "+r" (__op1) \ + : \ + : "ra", "a2", "a3"); \ + __op0; \ + }) +#endif /* __riscv_mul */ +#define umul_ppmm(w1, w0, u, v) \ + do { \ + UWtype __x0, __x1, __x2, __x3; \ + UHWtype __ul, __vl, __uh, __vh; \ + \ + __ul = __ll_lowpart (u); \ + __uh = __ll_highpart (u); \ + __vl = __ll_lowpart (v); \ + __vh = __ll_highpart (v); \ + \ + __x0 = __muluw3 (__ul, __vl); \ + __x1 = __muluw3 (__ul, __vh); \ + __x2 = __muluw3 (__uh, __vl); \ + __x3 = __muluw3 (__uh, __vh); \ + \ + __x1 += __ll_highpart (__x0);/* this can't give carry */ \ + __x1 += __x2; /* but this indeed can */ \ + if (__x1 < __x2) /* did we get it? */ \ + __x3 += __ll_B; /* yes, add it in the proper pos. */ \ + \ + (w1) = __x3 + __ll_highpart (__x1); \ + (w0) = __muluw3 (__ll_lowpart (__x1), __ll_B) \ + + __ll_lowpart (__x0); \ + } while (0) +#endif /* __riscv */ + #if defined(__sh__) && W_TYPE_SIZE == 32 #ifndef __sh1__ #define umul_ppmm(w1, w0, u, v) \