| Message ID | 20171002132032.GA21840@arm.com |
|---|---|
| State | New |
| Headers | show |
| Series | [testsuite,mid-end] Fix failing slp test on aarch64 and arm. | expand |
On 02/10/17 14:20, Tamar Christina wrote: > Hi All, > > The slp vectorization test currently fails on AArch32 and AArch64 > due to it not taking into account that we do have 128 bit vectors in > NEON. This means that two of the loops get vectorized instead of just 1. > > So update the conditions to include a check for neon. > > Regtested on aarch64-none-elf. > > Respin of patch https://gcc.gnu.org/ml/gcc-patches/2017-09/msg01805.html > > Ok for trunk? > > Thanks, > Tamar. > > gcc/testsuite/ > 2017-10-02 Tamar Christina <tamar.christina@arm.com> > > * gcc.dg/vect/slp-perm-9.c: Use vect_sizes_16B_8B. > * lib/target-supports.exp (vect_sizes_16B_8B): New. > > gcc/doc > > * sourcebuild.texi (vect_sizes_16B_8B, vect_sizes_32B_16B): New. > OK. R. > > 8221-diff.patch > > > diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi > index 56e1b4eb103ab412b29d6dcd9b556515ebc2ac63..98cebf7b58798abdcaa108daadcd6273667dc785 100644 > --- a/gcc/doc/sourcebuild.texi > +++ b/gcc/doc/sourcebuild.texi > @@ -1507,6 +1507,12 @@ Target supports conversion from @code{float} to @code{unsigned int}. > > @item vect_max_reduc > Target supports max reduction for vectors. > + > +@item vect_sizes_16B_8B > +Target supports 16- and 8-bytes vectors. > + > +@item vect_sizes_32B_16B > +Target supports 32- and 16-bytes vectors. > @end table > > @subsubsection Thread Local Storage attributes > diff --git a/gcc/testsuite/gcc.dg/vect/slp-perm-9.c b/gcc/testsuite/gcc.dg/vect/slp-perm-9.c > index 4d9c11dcc476a8023b3eaac2ae76cc01bd0db182..b9b5a3b87ad031a5ab7421efce2c2b0fdf9145f3 100644 > --- a/gcc/testsuite/gcc.dg/vect/slp-perm-9.c > +++ b/gcc/testsuite/gcc.dg/vect/slp-perm-9.c > @@ -54,8 +54,8 @@ int main (int argc, const char* argv[]) > return 0; > } > > -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { {! vect_perm } || {! vect_sizes_32B_16B } } } } } */ > -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { { vect_perm } && { vect_sizes_32B_16B } } } } } */ > +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { {! vect_perm } || {! vect_sizes_16B_8B } } } } } */ > +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { { vect_perm } && { vect_sizes_16B_8B } } } } } */ > /* { dg-final { scan-tree-dump-times "permutation requires at least three vectors" 1 "vect" { target vect_perm_short } } } */ > /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { {! vect_perm } || {! vect_sizes_32B_16B } } } } } */ > /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { { vect_perm } && { vect_sizes_32B_16B } } } } } */ > diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp > index 57f646ce2df5bcd5619870403242e73f6e91ff77..8ad9b602d277c28a6e34942a564d2ce05da7857f 100644 > --- a/gcc/testsuite/lib/target-supports.exp > +++ b/gcc/testsuite/lib/target-supports.exp > @@ -7561,6 +7561,19 @@ proc check_effective_target_vect_sizes_32B_16B { } { > } > } > > +# Return true if 16- and 8-bytes vectors are available. > + > +proc check_effective_target_vect_sizes_16B_8B { } { > + if { [check_avx_available] > + || [is-effective-target arm_neon] > + || [istarget aarch64*-*-*] } { > + return 1; > + } else { > + return 0; > + } > +} > + > + > # Return true if 128-bits vectors are preferred even if 256-bits vectors > # are available. > >
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 56e1b4eb103ab412b29d6dcd9b556515ebc2ac63..98cebf7b58798abdcaa108daadcd6273667dc785 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -1507,6 +1507,12 @@ Target supports conversion from @code{float} to @code{unsigned int}. @item vect_max_reduc Target supports max reduction for vectors. + +@item vect_sizes_16B_8B +Target supports 16- and 8-bytes vectors. + +@item vect_sizes_32B_16B +Target supports 32- and 16-bytes vectors. @end table @subsubsection Thread Local Storage attributes diff --git a/gcc/testsuite/gcc.dg/vect/slp-perm-9.c b/gcc/testsuite/gcc.dg/vect/slp-perm-9.c index 4d9c11dcc476a8023b3eaac2ae76cc01bd0db182..b9b5a3b87ad031a5ab7421efce2c2b0fdf9145f3 100644 --- a/gcc/testsuite/gcc.dg/vect/slp-perm-9.c +++ b/gcc/testsuite/gcc.dg/vect/slp-perm-9.c @@ -54,8 +54,8 @@ int main (int argc, const char* argv[]) return 0; } -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { {! vect_perm } || {! vect_sizes_32B_16B } } } } } */ -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { { vect_perm } && { vect_sizes_32B_16B } } } } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { {! vect_perm } || {! vect_sizes_16B_8B } } } } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { { vect_perm } && { vect_sizes_16B_8B } } } } } */ /* { dg-final { scan-tree-dump-times "permutation requires at least three vectors" 1 "vect" { target vect_perm_short } } } */ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 0 "vect" { target { {! vect_perm } || {! vect_sizes_32B_16B } } } } } */ /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { { vect_perm } && { vect_sizes_32B_16B } } } } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 57f646ce2df5bcd5619870403242e73f6e91ff77..8ad9b602d277c28a6e34942a564d2ce05da7857f 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -7561,6 +7561,19 @@ proc check_effective_target_vect_sizes_32B_16B { } { } } +# Return true if 16- and 8-bytes vectors are available. + +proc check_effective_target_vect_sizes_16B_8B { } { + if { [check_avx_available] + || [is-effective-target arm_neon] + || [istarget aarch64*-*-*] } { + return 1; + } else { + return 0; + } +} + + # Return true if 128-bits vectors are preferred even if 256-bits vectors # are available.