From patchwork Tue Sep 26 10:37:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andreas Krebbel X-Patchwork-Id: 818515 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-462948-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="lXqO+6QS"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3y1crC11gfz9t6C for ; Tue, 26 Sep 2017 20:38:50 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:in-reply-to:references:message-id; q=dns; s= default; b=s0+o97m+eVjULM6nYskZkW6l73TXpSS7F++Ui7oX8ulQjAKVxtyYk HYxrhUzqOMCnEV5trzhiyM9WhT5Detbz+Ji2sptJL9dpsWkBymrKA4KZXFNvHgld f7bbmsX2/QKtDSaDHNz5sEr/n1WeNLknVvjnhzvxYM1y6Yj9g9vrxo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:in-reply-to:references:message-id; s=default; bh=JNsKQaykdfkoajl0TMgKGzLOcpM=; b=lXqO+6QSQsdU4Dw6wUC/kUvJo6FI BqH5xGP7mrX+eS6DOLWdINY9EdMiWmByAyPuf3yOuig0eGa3hssShb9Y8QY7rxoE 0dzX2uxsbp7X9c1KbtrJHfEYGOQTtjgluk3z9trGYRDZkypmz4bsBS+GXYFt25jA uOitf/jp8QVvhz8= Received: (qmail 102514 invoked by alias); 26 Sep 2017 10:38:07 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 102434 invoked by uid 89); 26 Sep 2017 10:38:07 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.6 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.2 spammy= X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 26 Sep 2017 10:38:05 +0000 Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v8QAbcfY113921 for ; Tue, 26 Sep 2017 06:38:00 -0400 Received: from e06smtp12.uk.ibm.com (e06smtp12.uk.ibm.com [195.75.94.108]) by mx0a-001b2d01.pphosted.com with ESMTP id 2d7k4h8g82-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Tue, 26 Sep 2017 06:38:00 -0400 Received: from localhost by e06smtp12.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 26 Sep 2017 11:37:56 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v8QAbudw21627098 for ; Tue, 26 Sep 2017 10:37:56 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9E3AC52041 for ; Tue, 26 Sep 2017 10:32:46 +0100 (BST) Received: from maggie.boeblingen.de.ibm.com (unknown [9.152.212.134]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTPS id 83FB65203F for ; Tue, 26 Sep 2017 10:32:46 +0100 (BST) From: Andreas Krebbel To: gcc-patches@gcc.gnu.org Subject: [PATCH 4/8] S/390: Add FP vec_pack/unpack Date: Tue, 26 Sep 2017 12:37:47 +0200 In-Reply-To: <20170926103751.21907-1-krebbel@linux.vnet.ibm.com> References: <20170926103751.21907-1-krebbel@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 17092610-0008-0000-0000-0000049A254E X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17092610-0009-0000-0000-00001E2B6F31 Message-Id: <20170926103751.21907-5-krebbel@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-09-26_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=1 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1709260158 X-IsSubscribed: yes gcc/ChangeLog: 2017-09-26 Andreas Krebbel * config/s390/vector.md ("vec_unpacks_lo_v4sf") ("vec_unpacks_hi_v4sf", "vec_unpacks_lo_v2df") ("vec_unpacks_hi_v2df", "vec_pack_trunc_v2df"): New expanders. --- gcc/ChangeLog | 6 +++ gcc/config/s390/vector.md | 96 ++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 101 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7843857..d2808b5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2017-09-26 Andreas Krebbel + * config/s390/vector.md ("vec_unpacks_lo_v4sf") + ("vec_unpacks_hi_v4sf", "vec_unpacks_lo_v2df") + ("vec_unpacks_hi_v2df", "vec_pack_trunc_v2df"): New expanders. + +2017-09-26 Andreas Krebbel + * config/s390/predicates.md ("const_shift_by_byte_operand"): New predicate. * config/s390/vector.md ("*vec_srb"): Change modes to V_128 diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index e61bb88..c15d81d 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -1781,7 +1781,7 @@ ;; vector load lengthened -; vflls +; vflls float -> double (define_insn "*vec_extendv4sf" [(set (match_operand:V2DF 0 "register_operand" "=v") (float_extend:V2DF @@ -1792,6 +1792,34 @@ "vldeb\t%v0,%v1" [(set_attr "op_type" "VRR")]) +(define_expand "vec_unpacks_lo_v4sf" + [(set (match_dup 2) + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") + (match_dup 1)] + UNSPEC_VEC_MERGEL)) + (set (match_operand:V2DF 0 "register_operand" "=v") + (float_extend:V2DF + (vec_select:V2SF + (match_dup 2) + (parallel [(const_int 0) (const_int 2)]))))] + "TARGET_VX" +{ operands[2] = gen_reg_rtx(V4SFmode); }) + +(define_expand "vec_unpacks_hi_v4sf" + [(set (match_dup 2) + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") + (match_dup 1)] + UNSPEC_VEC_MERGEH)) + (set (match_operand:V2DF 0 "register_operand" "=v") + (float_extend:V2DF + (vec_select:V2SF + (match_dup 2) + (parallel [(const_int 0) (const_int 2)]))))] + "TARGET_VX" +{ operands[2] = gen_reg_rtx(V4SFmode); }) + + +; double -> long double (define_insn "*vec_extendv2df" [(set (match_operand:V1TF 0 "register_operand" "=v") (float_extend:V1TF @@ -1802,6 +1830,72 @@ "wflld\t%v0,%v1" [(set_attr "op_type" "VRR")]) +(define_expand "vec_unpacks_lo_v2df" + [(set (match_dup 2) + (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "v") + (match_dup 1)] + UNSPEC_VEC_MERGEL)) + (set (match_operand:V1TF 0 "register_operand" "=v") + (float_extend:V1TF + (vec_select:V1DF + (match_dup 2) + (parallel [(const_int 0)]))))] + "TARGET_VXE" +{ operands[2] = gen_reg_rtx (V2DFmode); }) + +(define_expand "vec_unpacks_hi_v2df" + [(set (match_dup 2) + (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "v") + (match_dup 1)] + UNSPEC_VEC_MERGEH)) + (set (match_operand:V1TF 0 "register_operand" "=v") + (float_extend:V1TF + (vec_select:V1DF + (match_dup 2) + (parallel [(const_int 0)]))))] + "TARGET_VXE" +{ operands[2] = gen_reg_rtx (V2DFmode); }) + + +; 2 x v2df -> 1 x v4sf +(define_expand "vec_pack_trunc_v2df" + [(set (match_dup 3) + (unspec:V4SF [(match_operand:V2DF 1 "register_operand" "") + (const_int VEC_INEXACT) + (const_int VEC_RND_CURRENT)] + UNSPEC_VEC_VFLR)) + (set (match_dup 4) + (unspec:V4SF [(match_operand:V2DF 2 "register_operand" "") + (const_int VEC_INEXACT) + (const_int VEC_RND_CURRENT)] + UNSPEC_VEC_VFLR)) + (set (match_dup 6) + (unspec:V16QI [(subreg:V16QI (match_dup 3) 0) + (subreg:V16QI (match_dup 4) 0) + (match_dup 5)] + UNSPEC_VEC_PERM)) + (set (match_operand:V4SF 0 "register_operand" "") + (subreg:V4SF (match_dup 6) 0))] + "TARGET_VX" +{ + rtx constv, perm[16]; + int i; + + for (i = 0; i < 4; ++i) + { + perm[i] = GEN_INT (i); + perm[i + 4] = GEN_INT (i + 8); + perm[i + 8] = GEN_INT (i + 16); + perm[i + 12] = GEN_INT (i + 24); + } + constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm)); + + operands[3] = gen_reg_rtx (V4SFmode); + operands[4] = gen_reg_rtx (V4SFmode); + operands[5] = force_reg (V16QImode, constv); + operands[6] = gen_reg_rtx (V16QImode); +}) + ; reduc_smin ; reduc_smax ; reduc_umin