From patchwork Wed Jul 26 08:53:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Huber X-Patchwork-Id: 793758 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-458991-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="e6f7xAwy"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xHTRC6G8Mz9sN7 for ; Wed, 26 Jul 2017 18:53:23 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=PIXY4BEvx8vS VGBx4zosjQblIoz827OzqyO0yYl8BELUMMCtBCV7dgEnP4eF36Olw+TdTRTS06yK z5YJAwjPFy7wti2+ZIvM9EyklTWQ3MLckzNvXByiTfCJobHE+9BZPppQ45m/HZyK j/oDSRp34wQSAsqoGEOpIUtEwd+SMuw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=zV9nJGFgg784dLTW8Y +wDWsA3bk=; b=e6f7xAwy5wG8jVbjEZY19aQ2Yp2b+hEpAoWAMONJmYlebuTJfB NT0yyXoUPRiC0fM6I+YVzrUe4o1ZAfmtRFt8LVtuX+UwO2lJAgN0BUJQdYdofQ2W 5kqnVk1Jv0ZlsQEk50j8sPgR+mI7+hmorCnPn58D6ERT1YKFaTYhTJr/M= Received: (qmail 70674 invoked by alias); 26 Jul 2017 08:53:10 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 70656 invoked by uid 89); 26 Jul 2017 08:53:09 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.6 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: dedi548.your-server.de Received: from dedi548.your-server.de (HELO dedi548.your-server.de) (85.10.215.148) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 26 Jul 2017 08:53:07 +0000 Received: from [88.198.220.131] (helo=sslproxy02.your-server.de) by dedi548.your-server.de with esmtpsa (TLSv1.2:DHE-RSA-AES256-GCM-SHA384:256) (Exim 4.85_2) (envelope-from ) id 1daI41-0004UK-C1; Wed, 26 Jul 2017 10:53:05 +0200 Received: from [82.135.62.35] (helo=mail.embedded-brains.de) by sslproxy02.your-server.de with esmtpsa (TLSv1.2:DHE-RSA-AES256-GCM-SHA384:256) (Exim 4.84_2) (envelope-from ) id 1daI41-0006wU-3Q; Wed, 26 Jul 2017 10:53:05 +0200 Received: from localhost (localhost.localhost [127.0.0.1]) by mail.embedded-brains.de (Postfix) with ESMTP id 369F22A004F; Wed, 26 Jul 2017 10:53:12 +0200 (CEST) Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id l9GiEbK7Ktoi; Wed, 26 Jul 2017 10:53:10 +0200 (CEST) Received: from localhost (localhost.localhost [127.0.0.1]) by mail.embedded-brains.de (Postfix) with ESMTP id 03C7D2A160A; Wed, 26 Jul 2017 10:53:10 +0200 (CEST) Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id Z7du7Z1Qq9Ts; Wed, 26 Jul 2017 10:53:09 +0200 (CEST) Received: from linux-diu0.suse (unknown [192.168.96.129]) by mail.embedded-brains.de (Postfix) with ESMTP id D8F962A004F; Wed, 26 Jul 2017 10:53:09 +0200 (CEST) From: Sebastian Huber To: gcc-patches@gcc.gnu.org Cc: software@gaisler.com Subject: [PATCH v2] [SPARC] Add -mfsmuld option Date: Wed, 26 Jul 2017 10:53:00 +0200 Message-Id: <20170726085300.14685-1-sebastian.huber@embedded-brains.de> X-IsSubscribed: yes Add the -mfsmuld option to control the generation of the FsMULd instruction. In general, this instruction is available in architecture version V8 and V9 CPUs with FPU. Some CPUs of this category do not support this instruction properly, e.g. AT697E, AT697F and UT699. Some CPUs of this category do not implement it in hardware, e.g. LEON3/4 with GRFPU-lite. gcc/ * config/sparc/sparc.c (dump_target_flag_bits): Dump MASK_FSMULD. (sparc_option_override): Honour MASK_FSMULD. * config/sparc/sparc.h (MASK_FEATURES): Add MASK_FSMULD. * config/sparc/sparc.md (muldf3_extend): Use TARGET_FSMULD. * config/sparc/sparc.opt (mfsmuld): New option. * doc/invoke.texi (mfsmuld): Document option. --- gcc/config/sparc/sparc.c | 30 ++++++++++++++++++++---------- gcc/config/sparc/sparc.h | 3 ++- gcc/config/sparc/sparc.md | 2 +- gcc/config/sparc/sparc.opt | 4 ++++ gcc/doc/invoke.texi | 11 ++++++++++- 5 files changed, 37 insertions(+), 13 deletions(-) diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 674a3823cb9..8eed2fc5621 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -1304,6 +1304,8 @@ dump_target_flag_bits (const int flags) fprintf (stderr, "FLAT "); if (flags & MASK_FMAF) fprintf (stderr, "FMAF "); + if (flags & MASK_FSMULD) + fprintf (stderr, "FSMULD "); if (flags & MASK_FPU) fprintf (stderr, "FPU "); if (flags & MASK_HARD_QUAD) @@ -1403,24 +1405,24 @@ sparc_option_override (void) const int disable; const int enable; } const cpu_table[] = { - { "v7", MASK_ISA, 0 }, - { "cypress", MASK_ISA, 0 }, + { "v7", MASK_ISA|MASK_FSMULD, 0 }, + { "cypress", MASK_ISA|MASK_FSMULD, 0 }, { "v8", MASK_ISA, MASK_V8 }, /* TI TMS390Z55 supersparc */ { "supersparc", MASK_ISA, MASK_V8 }, { "hypersparc", MASK_ISA, MASK_V8 }, - { "leon", MASK_ISA, MASK_V8|MASK_LEON }, + { "leon", MASK_ISA|MASK_FSMULD, MASK_V8|MASK_LEON }, { "leon3", MASK_ISA, MASK_V8|MASK_LEON3 }, - { "leon3v7", MASK_ISA, MASK_LEON3 }, - { "sparclite", MASK_ISA, MASK_SPARCLITE }, + { "leon3v7", MASK_ISA|MASK_FSMULD, MASK_LEON3 }, + { "sparclite", MASK_ISA|MASK_FSMULD, MASK_SPARCLITE }, /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */ { "f930", MASK_ISA|MASK_FPU, MASK_SPARCLITE }, /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */ - { "f934", MASK_ISA, MASK_SPARCLITE }, + { "f934", MASK_ISA|MASK_FSMULD, MASK_SPARCLITE }, { "sparclite86x", MASK_ISA|MASK_FPU, MASK_SPARCLITE }, - { "sparclet", MASK_ISA, MASK_SPARCLET }, + { "sparclet", MASK_ISA|MASK_FSMULD, MASK_SPARCLET }, /* TEMIC sparclet */ - { "tsc701", MASK_ISA, MASK_SPARCLET }, + { "tsc701", MASK_ISA|MASK_FSMULD, MASK_SPARCLET }, { "v9", MASK_ISA, MASK_V9 }, /* UltraSPARC I, II, IIi */ { "ultrasparc", MASK_ISA, @@ -1511,6 +1513,11 @@ sparc_option_override (void) target_flags |= MASK_LONG_DOUBLE_128; } + /* Enable the FSMULD instruction by default if not explicitly configured by + the user. It may be later disabled by the CPU target flags or if + !TARGET_FPU. */ + target_flags |= MASK_FSMULD & ~target_flags_explicit; + /* Code model selection. */ sparc_cmodel = SPARC_DEFAULT_CMODEL; @@ -1603,11 +1610,11 @@ sparc_option_override (void) if (TARGET_VIS4B) target_flags |= MASK_VIS4 | MASK_VIS3 | MASK_VIS2 | MASK_VIS; - /* Don't allow -mvis, -mvis2, -mvis3, -mvis4, -mvis4b and -mfmaf if + /* Don't allow -mvis, -mvis2, -mvis3, -mvis4, -mvis4b, -mfmaf and -mfsmuld if FPU is disabled. */ if (! TARGET_FPU) target_flags &= ~(MASK_VIS | MASK_VIS2 | MASK_VIS3 | MASK_VIS4 - | MASK_VIS4B | MASK_FMAF); + | MASK_VIS4B | MASK_FMAF | MASK_FSMULD); /* -mvis assumes UltraSPARC+, so we are sure v9 instructions are available; -m64 also implies v9. */ @@ -1641,6 +1648,9 @@ sparc_option_override (void) if (sparc_fix_ut699 || sparc_fix_ut700 || sparc_fix_gr712rc) sparc_fix_b2bst = 1; + if (sparc_fix_ut699) + target_flags &= ~MASK_FSMULD; + /* Supply a default value for align_functions. */ if (align_functions == 0) { diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index d7c617e06c3..15a62179af5 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -438,7 +438,8 @@ extern enum cmodel sparc_cmodel; /* Mask of all CPU feature flags. */ #define MASK_FEATURES \ (MASK_FPU + MASK_HARD_QUAD + MASK_VIS + MASK_VIS2 + MASK_VIS3 \ - + MASK_VIS4 + MASK_CBCOND + MASK_FMAF + MASK_POPC + MASK_SUBXC) + + MASK_VIS4 + MASK_CBCOND + MASK_FMAF + MASK_FSMULD \ + + MASK_POPC + MASK_SUBXC) /* TARGET_HARD_MUL: Use 32-bit hardware multiply instructions but not %y. */ #define TARGET_HARD_MUL \ diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index b154003c54a..751bacdbcac 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -6121,7 +6121,7 @@ visl") [(set (match_operand:DF 0 "register_operand" "=e") (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "f")) (float_extend:DF (match_operand:SF 2 "register_operand" "f"))))] - "(TARGET_V8 || TARGET_V9) && TARGET_FPU && !sparc_fix_ut699" + "TARGET_FSMULD" "fsmuld\t%1, %2, %0" [(set_attr "type" "fpmul") (set_attr "fptype" "double")]) diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt index ae63d2018e3..22267f50e90 100644 --- a/gcc/config/sparc/sparc.opt +++ b/gcc/config/sparc/sparc.opt @@ -93,6 +93,10 @@ mfmaf Target Report Mask(FMAF) Use UltraSPARC Fused Multiply-Add extensions. +mfsmuld +Target Report Mask(FSMULD) +Use Floating-point Multiply Single to Double (FsMULd) instruction. + mpopc Target Report Mask(POPC) Use UltraSPARC Population-Count instruction. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index a6da37c8203..6e174c5b3ff 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1124,7 +1124,7 @@ See RS/6000 and PowerPC Options. -mv8plus -mno-v8plus -mvis -mno-vis @gol -mvis2 -mno-vis2 -mvis3 -mno-vis3 @gol -mvis4 -mno-vis4 -mvis4b -mno-vis4b @gol --mcbcond -mno-cbcond -mfmaf -mno-fmaf @gol +-mcbcond -mno-cbcond -mfmaf -mno-fmaf -mfsmuld -mno-fsmuld @gol -mpopc -mno-popc -msubxc -mno-subxc @gol -mfix-at697f -mfix-ut699 -mfix-ut700 -mfix-gr712rc @gol -mlra -mno-lra} @@ -24069,6 +24069,15 @@ Fused Multiply-Add Floating-point instructions. The default is @option{-mfmaf} when targeting a CPU that supports such instructions, such as Niagara-3 and later. +@item -mfsmuld +@itemx -mno-fsmuld +@opindex mfsmuld +@opindex mno-fsmuld +With @option{-mfsmuld}, GCC generates code that takes advantage of the +Floating-point Multiply Single to Double (FsMULd) instruction. The default is +@option{-mfsmuld} when targeting a CPU supporting the architecture versions V8 +or V9 with FPU except @option{-mcpu=leon}. + @item -mpopc @itemx -mno-popc @opindex mpopc