From patchwork Wed Jul 26 04:24:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 793703 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-458971-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="igYK/x4j"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xHMXD2fkSz9s7M for ; Wed, 26 Jul 2017 14:27:24 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:references:mime-version:content-type :in-reply-to:message-id; q=dns; s=default; b=T1qFHA3pjBCqdIwKX6I UJNF9Lw0BIr6pKPXOAJbzorSoeSShZHUgeAAnn3/CNYG2FESNSqhvKgwqA/1jB6G peSAi985FGURRKIjn5B+gZ8ojRvu4XInn2R8VxAjPsvWTqoqCwrPwqot1BC6aito 5OwPhziDYWnz1z5znzWcuKjo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:references:mime-version:content-type :in-reply-to:message-id; s=default; bh=VcDC29GlolaUkSrOxFGRVYgua xo=; b=igYK/x4jERWQ80GrTzGc3HK/yM36BKkBs6iL679Hyn0P22gA9r29agoHJ ooCNoZSkxoUL28E+NfLywWuuBPwZtXq9lI5RjgzgQSQ7Z0M6Zz2d8vVyENmvtRjM dhSY6IAhw6h6/h+P7HrsKvzL2k8xlGLxLp51xmZApkdogzIJdg= Received: (qmail 40340 invoked by alias); 26 Jul 2017 04:27:03 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 101973 invoked by uid 89); 26 Jul 2017 04:24:54 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-9.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_LOW, TVD_SUBJ_WIPE_DEBT autolearn=ham version=3.3.2 spammy=bh X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 26 Jul 2017 04:24:26 +0000 Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v6Q4NY1k012355 for ; Wed, 26 Jul 2017 00:24:22 -0400 Received: from e35.co.us.ibm.com (e35.co.us.ibm.com [32.97.110.153]) by mx0a-001b2d01.pphosted.com with ESMTP id 2bxj8k3rvs-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 26 Jul 2017 00:24:22 -0400 Received: from localhost by e35.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 25 Jul 2017 22:24:19 -0600 Received: from b03ledav004.gho.boulder.ibm.com (b03ledav004.gho.boulder.ibm.com [9.17.130.235]) by b03cxnp07028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v6Q4OGFW4194790; Tue, 25 Jul 2017 21:24:18 -0700 Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8F97F78037; Tue, 25 Jul 2017 22:24:18 -0600 (MDT) Received: from ibm-tiger.the-meissners.org (unknown [9.32.77.111]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP id 638F678038; Tue, 25 Jul 2017 22:24:18 -0600 (MDT) Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id CE3DE476D6; Wed, 26 Jul 2017 00:24:17 -0400 (EDT) Date: Wed, 26 Jul 2017 00:24:17 -0400 From: Michael Meissner To: Michael Meissner , Segher Boessenkool , GCC Patches , David Edelsohn , Bill Schmidt Subject: Re: [PATCH #4, cleanup] Remove PowerPC -mvsx-small-integer Mail-Followup-To: Michael Meissner , Segher Boessenkool , GCC Patches , David Edelsohn , Bill Schmidt References: <20170722064604.GA19115@ibm-tiger.the-meissners.org> <20170724102115.GW13471@gate.crashing.org> <20170724200645.GA7617@ibm-tiger.the-meissners.org> <20170724205112.GC13471@gate.crashing.org> <20170724234025.GA9424@ibm-tiger.the-meissners.org> <20170725123446.GF13471@gate.crashing.org> <20170725131725.GA15369@ibm-tiger.the-meissners.org> <20170725223911.GL13471@gate.crashing.org> <20170726042318.GA18770@ibm-tiger.the-meissners.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20170726042318.GA18770@ibm-tiger.the-meissners.org> User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-GCONF: 00 x-cbid: 17072604-0012-0000-0000-000014BC289A X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007427; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000214; SDB=6.00892985; UDB=6.00446390; IPR=6.00673149; BA=6.00005492; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00016381; XFM=3.00000015; UTC=2017-07-26 04:24:20 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17072604-0013-0000-0000-00004EC5B762 Message-Id: <20170726042417.GB18770@ibm-tiger.the-meissners.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-07-26_02:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1706020000 definitions=main-1707260065 X-IsSubscribed: yes I forgot to include the patch for these changes: [gcc] 2017-07-25 Michael Meissner * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Delete -mvsx-small-integer option. (ISA_3_0_MASKS_IEEE): Likewise. (POWERPC_MASKS): Likewise. * config/rs6000/rs6000.opt (-mvsx-small-integer): Likewise. * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Simplify code, only testing for DImode being allowed in non-VSX floating point registers. (rs6000_init_hard_regno_mode_ok): Change TARGET_VSX_SMALL_INTEGER to TARGET_P8_VECTOR test. Remove redundant VSX test inside of another VSX test. (rs6000_option_override_internal): Delete -mvsx-small-integer. (rs6000_expand_vector_set): Change TARGET_VSX_SMALL_INTEGER to TARGET_P8_VECTOR test. (rs6000_secondary_reload_simple_move): Likewise. (rs6000_preferred_reload_class): Delete TARGET_VSX_SMALL_INTEGER, since TARGET_P9_VECTOR was already tested. (rs6000_opt_masks): Remove -mvsx-small-integer. * config/rs6000/vsx.md (vsx_extract_): Delete TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was used. (vsx_extract__p9): Delete TARGET_VSX_SMALL_INTEGER, since a test for TARGET_VEXTRACTUB was used, and that uses TARGET_P9_VECTOR. (p9 extract splitter): Likewise. (vsx_extract__di_p9): Likewise. (vsx_extract__store_p9): Likewise. (vsx_extract_si): Delete TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was used. Delete code that is now dead with the elimination of TARGET_VSX_SMALL_INTEGER. (vsx_extract__p8): Likewise. (vsx_ext__fl_): Likewise. (vsx_ext__ufl_): Likewise. (vsx_set__p9): Likewise. (vsx_set_v4sf_p9): Likewise. (vsx_set_v4sf_p9_zero): Likewise. (vsx_insert_extract_v4sf_p9): Likewise. (vsx_insert_extract_v4sf_p9_2): Likewise. * config/rs6000/rs6000.md (sign extend splitter): Change TARGET_VSX_SMALL_INTEGER to TARGET_P8_VECTOR test. (floatsi2_lfiwax_mem): Likewise. (floatunssi2_lfiwzx_mem): Likewise. (float2): Delete TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was used. (float2_internal): Likewise. (floatuns2): Likewise. (floatuns2_internal): Likewise. (fix_truncsi2): Change TARGET_VSX_SMALL_INTEGER to TARGET_P8_VECTOR test. (fix_truncsi2_stfiwx): Likewise. (fix_truncsi2_internal): Likewise. (fix_trunc2): Delete TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was used. (fix_trunc2_internal): Likewise. (fixuns_truncsi2): Change TARGET_VSX_SMALL_INTEGER to TARGET_P8_VECTOR test. (fixuns_truncsi2_stfiwx): Likewise. (fixuns_trunc2): Delete TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was used. (fixuns_trunc2_internal): Likewise. (fctiwz__smallint): Delete TARGET_VSX_SMALL_INTEGER, since a test for TARGET_P9_VECTOR was used. (splitter for loading small constants): Likewise. [gcc/testsuite] 2017-07-25 Michael Meissner * gcc.target/powerpc/vsx-himode.c: Delete -mvsx-small-integer option. * gcc.target/powerpc/vsx-himode2.c: Likewise. * gcc.target/powerpc/vsx-himode3.c: Likewise. * gcc.target/powerpc/vsx-qimode.c: Likewise. * gcc.target/powerpc/vsx-qimode2.c: Likewise. * gcc.target/powerpc/vsx-qimode3.c: Likewise. * gcc.target/powerpc/vsx-simode.c: Likewise. * gcc.target/powerpc/vsx-simode2.c: Likewise. * gcc.target/powerpc/vsx-simode3.c: Likewise. Index: gcc/config/rs6000/rs6000-cpus.def =================================================================== --- gcc/config/rs6000/rs6000-cpus.def (revision 250485) +++ gcc/config/rs6000/rs6000-cpus.def (working copy) @@ -55,8 +55,7 @@ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_HTM \ | OPTION_MASK_QUAD_MEMORY \ - | OPTION_MASK_QUAD_MEMORY_ATOMIC \ - | OPTION_MASK_VSX_SMALL_INTEGER) + | OPTION_MASK_QUAD_MEMORY_ATOMIC) /* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add FLOAT128_HW here until we are ready to make -mfloat128 on by default. */ @@ -75,8 +74,7 @@ #define ISA_3_0_MASKS_IEEE (OPTION_MASK_VSX \ | OPTION_MASK_P8_VECTOR \ | OPTION_MASK_P9_VECTOR \ - | OPTION_MASK_DIRECT_MOVE \ - | OPTION_MASK_VSX_SMALL_INTEGER) + | OPTION_MASK_DIRECT_MOVE) /* Flags that need to be turned off if -mno-power9-vector. */ #define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \ @@ -96,7 +94,6 @@ | OPTION_MASK_FLOAT128_KEYWORD \ | OPTION_MASK_FLOAT128_TYPE \ | OPTION_MASK_P8_VECTOR \ - | OPTION_MASK_VSX_SMALL_INTEGER \ | OPTION_MASK_VSX_TIMODE) #define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC) @@ -152,7 +149,6 @@ | OPTION_MASK_STRICT_ALIGN_OPTIONAL \ | OPTION_MASK_TOC_FUSION \ | OPTION_MASK_VSX \ - | OPTION_MASK_VSX_SMALL_INTEGER \ | OPTION_MASK_VSX_TIMODE) #endif Index: gcc/config/rs6000/rs6000.opt =================================================================== --- gcc/config/rs6000/rs6000.opt (revision 250485) +++ gcc/config/rs6000/rs6000.opt (working copy) @@ -606,10 +606,6 @@ mfloat128-convert Target Undocumented Mask(FLOAT128_CVT) Var(rs6000_isa_flags) Enable default conversions between __float128 & long double. -mvsx-small-integer -Target Report Mask(VSX_SMALL_INTEGER) Var(rs6000_isa_flags) -Enable small integers to be in VSX registers. - mstack-protector-guard= Target RejectNegative Joined Enum(stack_protector_guard) Var(rs6000_stack_protector_guard) Init(SSP_TLS) Use given stack-protector guard. Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 250508) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -2099,20 +2099,8 @@ rs6000_hard_regno_mode_ok (int regno, ma && FP_REGNO_P (last_regno)) return 1; - if (GET_MODE_CLASS (mode) == MODE_INT) - { - if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD) - return 1; - - if (TARGET_VSX_SMALL_INTEGER) - { - if (mode == SImode) - return 1; - - if (TARGET_P9_VECTOR && (mode == HImode || mode == QImode)) - return 1; - } - } + if (mode == DImode) + return 1; if (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode)) @@ -3291,7 +3279,7 @@ rs6000_init_hard_regno_mode_ok (bool glo rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS; /* Support small integers in VSX registers. */ - if (TARGET_VSX_SMALL_INTEGER) + if (TARGET_P8_VECTOR) { rs6000_constraints[RS6000_CONSTRAINT_wH] = ALTIVEC_REGS; rs6000_constraints[RS6000_CONSTRAINT_wI] = FLOAT_REGS; @@ -3446,18 +3434,14 @@ rs6000_init_hard_regno_mode_ok (bool glo } } - if (TARGET_VSX) - { - reg_addr[DFmode].scalar_in_vmx_p = true; - reg_addr[DImode].scalar_in_vmx_p = true; - } + reg_addr[DFmode].scalar_in_vmx_p = true; + reg_addr[DImode].scalar_in_vmx_p = true; if (TARGET_P8_VECTOR) - reg_addr[SFmode].scalar_in_vmx_p = true; - - if (TARGET_VSX_SMALL_INTEGER) { + reg_addr[SFmode].scalar_in_vmx_p = true; reg_addr[SImode].scalar_in_vmx_p = true; + if (TARGET_P9_VECTOR) { reg_addr[HImode].scalar_in_vmx_p = true; @@ -4632,20 +4616,6 @@ rs6000_option_override_internal (bool gl } } - /* Check whether we should allow small integers into VSX registers. We - require direct move to prevent the register allocator from having to move - variables through memory to do moves. SImode can be used on ISA 2.07, - while HImode and QImode require ISA 3.0. */ - if (TARGET_VSX_SMALL_INTEGER - && (!TARGET_DIRECT_MOVE || !TARGET_P8_VECTOR)) - { - if (rs6000_isa_flags_explicit & OPTION_MASK_VSX_SMALL_INTEGER) - error ("-mvsx-small-integer requires -mpower8-vector, " - "and -mdirect-move"); - - rs6000_isa_flags &= ~OPTION_MASK_VSX_SMALL_INTEGER; - } - /* Set long double size before the IEEE 128-bit tests. */ if (!global_options_set.x_rs6000_long_double_type_size) { @@ -7338,7 +7308,7 @@ rs6000_expand_vector_set (rtx target, rt else if (mode == V2DImode) insn = gen_vsx_set_v2di (target, target, val, elt_rtx); - else if (TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER && TARGET_POWERPC64) + else if (TARGET_P9_VECTOR && TARGET_POWERPC64) { if (mode == V4SImode) insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx); @@ -19713,7 +19683,7 @@ rs6000_secondary_reload_simple_move (enu } /* ISA 2.07: MTVSRWZ or MFVSRWZ. */ - if (TARGET_VSX_SMALL_INTEGER) + if (TARGET_P8_VECTOR) { if (mode == SImode) return true; @@ -20547,7 +20517,6 @@ rs6000_preferred_reload_class (rtx x, en /* ISA 3.0 can load -128..127 using the XXSPLTIB instruction and a sign extend in the Altivec registers. */ if (IN_RANGE (value, -128, 127) && TARGET_P9_VECTOR - && TARGET_VSX_SMALL_INTEGER && (rclass == ALTIVEC_REGS || rclass == VSX_REGS)) return ALTIVEC_REGS; } @@ -36255,7 +36224,6 @@ static struct rs6000_opt_mask const rs60 { "toc-fusion", OPTION_MASK_TOC_FUSION, false, true }, { "update", OPTION_MASK_NO_UPDATE, true , true }, { "vsx", OPTION_MASK_VSX, false, true }, - { "vsx-small-integer", OPTION_MASK_VSX_SMALL_INTEGER, false, true }, { "vsx-timode", OPTION_MASK_VSX_TIMODE, false, true }, #ifdef OPTION_MASK_64BIT #if TARGET_AIX_OS Index: gcc/config/rs6000/vsx.md =================================================================== --- gcc/config/rs6000/vsx.md (revision 250508) +++ gcc/config/rs6000/vsx.md (working copy) @@ -2938,7 +2938,7 @@ (define_expand "vsx_extract_" "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT" { /* If we have ISA 3.0, we can do a xxextractuw/vextractu{b,h}. */ - if (TARGET_VSX_SMALL_INTEGER && TARGET_P9_VECTOR) + if (TARGET_P9_VECTOR) { emit_insn (gen_vsx_extract__p9 (operands[0], operands[1], operands[2])); @@ -2952,8 +2952,7 @@ (define_insn "vsx_extract__p9" (match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "wK,") (parallel [(match_operand:QI 2 "" "n,n")]))) (clobber (match_scratch:SI 3 "=r,X"))] - "VECTOR_MEM_VSX_P (mode) && TARGET_VEXTRACTUB - && TARGET_VSX_SMALL_INTEGER" + "VECTOR_MEM_VSX_P (mode) && TARGET_VEXTRACTUB" { if (which_alternative == 0) return "#"; @@ -2983,8 +2982,7 @@ (define_split (match_operand:VSX_EXTRACT_I 1 "altivec_register_operand") (parallel [(match_operand:QI 2 "const_int_operand")]))) (clobber (match_operand:SI 3 "int_reg_operand"))] - "VECTOR_MEM_VSX_P (mode) && TARGET_VEXTRACTUB - && TARGET_VSX_SMALL_INTEGER && reload_completed" + "VECTOR_MEM_VSX_P (mode) && TARGET_VEXTRACTUB && reload_completed" [(const_int 0)] { rtx op0_si = gen_rtx_REG (SImode, REGNO (operands[0])); @@ -3009,8 +3007,7 @@ (define_insn_and_split "*vsx_extract_") (parallel [(match_operand:QI 2 "const_int_operand" "n,n")])))) (clobber (match_scratch:SI 3 "=r,X"))] - "VECTOR_MEM_VSX_P (mode) && TARGET_VEXTRACTUB - && TARGET_VSX_SMALL_INTEGER" + "VECTOR_MEM_VSX_P (mode) && TARGET_VEXTRACTUB" "#" "&& reload_completed" [(parallel [(set (match_dup 4) @@ -3030,8 +3027,7 @@ (define_insn_and_split "*vsx_extract_ 3 "=,&r")) (clobber (match_scratch:SI 4 "=X,&r"))] - "VECTOR_MEM_VSX_P (mode) && TARGET_VEXTRACTUB - && TARGET_VSX_SMALL_INTEGER" + "VECTOR_MEM_VSX_P (mode) && TARGET_VEXTRACTUB" "#" "&& reload_completed" [(parallel [(set (match_dup 3) @@ -3048,8 +3044,7 @@ (define_insn_and_split "*vsx_extract_si (match_operand:V4SI 1 "gpc_reg_operand" "wJv,wJv,wJv") (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")]))) (clobber (match_scratch:V4SI 3 "=wJv,wJv,wJv"))] - "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT - && (!TARGET_P9_VECTOR || !TARGET_VSX_SMALL_INTEGER)" + "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT && !TARGET_P9_VECTOR" "#" "&& reload_completed" [(const_int 0)] @@ -3067,15 +3062,7 @@ (define_insn_and_split "*vsx_extract_si instruction. */ value = INTVAL (element); if (value != 1) - { - if (TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER) - { - rtx si_tmp = gen_rtx_REG (SImode, REGNO (vec_tmp)); - emit_insn (gen_vsx_extract_v4si_p9 (si_tmp,src, element)); - } - else - emit_insn (gen_altivec_vspltw_direct (vec_tmp, src, element)); - } + emit_insn (gen_altivec_vspltw_direct (vec_tmp, src, element)); else vec_tmp = src; @@ -3084,13 +3071,13 @@ (define_insn_and_split "*vsx_extract_si if (can_create_pseudo_p ()) dest = rs6000_address_for_fpconvert (dest); - if (TARGET_VSX_SMALL_INTEGER) + if (TARGET_P8_VECTOR) emit_move_insn (dest, gen_rtx_REG (SImode, REGNO (vec_tmp))); else emit_insn (gen_stfiwx (dest, gen_rtx_REG (DImode, REGNO (vec_tmp)))); } - else if (TARGET_VSX_SMALL_INTEGER) + else if (TARGET_P8_VECTOR) emit_move_insn (dest, gen_rtx_REG (SImode, REGNO (vec_tmp))); else emit_move_insn (gen_rtx_REG (DImode, REGNO (dest)), @@ -3108,7 +3095,7 @@ (define_insn_and_split "*vsx_extract_" "n")]))) (clobber (match_scratch:VSX_EXTRACT_I2 3 "=v"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT - && (!TARGET_P9_VECTOR || !TARGET_VSX_SMALL_INTEGER)" + && !TARGET_P9_VECTOR" "#" "&& reload_completed" [(const_int 0)] @@ -3319,7 +3306,7 @@ (define_insn_and_split "*vsx_ext_ 3 "=v"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT - && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER" + && TARGET_P9_VECTOR" "#" "&& reload_completed" [(parallel [(set (match_dup 3) @@ -3343,7 +3330,7 @@ (define_insn_and_split "*vsx_ext_ 3 "=v"))] "VECTOR_MEM_VSX_P (mode) && TARGET_DIRECT_MOVE_64BIT - && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER" + && TARGET_P9_VECTOR" "#" "&& reload_completed" [(parallel [(set (match_dup 3) @@ -3365,8 +3352,7 @@ (define_insn "vsx_set__p9" (match_operand: 2 "gpc_reg_operand" "") (match_operand:QI 3 "" "n")] UNSPEC_VSX_SET))] - "VECTOR_MEM_VSX_P (mode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER - && TARGET_POWERPC64" + "VECTOR_MEM_VSX_P (mode) && TARGET_P9_VECTOR && TARGET_POWERPC64" { int ele = INTVAL (operands[3]); int nunits = GET_MODE_NUNITS (mode); @@ -3390,8 +3376,7 @@ (define_insn_and_split "vsx_set_v4sf_p9" (match_operand:QI 3 "const_0_to_3_operand" "n")] UNSPEC_VSX_SET)) (clobber (match_scratch:SI 4 "=&wJwK"))] - "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER - && TARGET_POWERPC64" + "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_POWERPC64" "#" "&& reload_completed" [(set (match_dup 5) @@ -3426,8 +3411,7 @@ (define_insn_and_split "*vsx_set_v4sf_p9 (match_operand:QI 3 "const_0_to_3_operand" "n")] UNSPEC_VSX_SET)) (clobber (match_scratch:SI 4 "=&wJwK"))] - "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER - && TARGET_POWERPC64" + "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_POWERPC64" "#" "&& reload_completed" [(set (match_dup 4) @@ -3457,8 +3441,7 @@ (define_insn "*vsx_insert_extract_v4sf_p [(match_operand:QI 3 "const_0_to_3_operand" "n")])) (match_operand:QI 4 "const_0_to_3_operand" "n")] UNSPEC_VSX_SET))] - "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER - && TARGET_POWERPC64 + "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_POWERPC64 && (INTVAL (operands[3]) == (VECTOR_ELT_ORDER_BIG ? 1 : 2))" { int ele = INTVAL (operands[4]); @@ -3486,7 +3469,7 @@ (define_insn_and_split "*vsx_insert_extr UNSPEC_VSX_SET)) (clobber (match_scratch:SI 5 "=&wJwK"))] "VECTOR_MEM_VSX_P (V4SFmode) && VECTOR_MEM_VSX_P (V4SImode) - && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER && TARGET_POWERPC64 + && TARGET_P9_VECTOR && TARGET_POWERPC64 && (INTVAL (operands[3]) != (VECTOR_ELT_ORDER_BIG ? 1 : 2))" "#" "&& 1" Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 250508) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -1004,8 +1004,7 @@ (define_insn "extendsi2" (define_split [(set (match_operand:DI 0 "altivec_register_operand") (sign_extend:DI (match_operand:SI 1 "altivec_register_operand")))] - "TARGET_VSX_SMALL_INTEGER && TARGET_P8_VECTOR && !TARGET_P9_VECTOR - && reload_completed" + "TARGET_P8_VECTOR && !TARGET_P9_VECTOR && reload_completed" [(const_int 0)] { rtx dest = operands[0]; @@ -5161,7 +5160,7 @@ (define_insn_and_split "floatsi2_l operands[1] = rs6000_address_for_fpconvert (operands[1]); if (GET_CODE (operands[2]) == SCRATCH) operands[2] = gen_reg_rtx (DImode); - if (TARGET_VSX_SMALL_INTEGER) + if (TARGET_P8_VECTOR) emit_insn (gen_extendsidi2 (operands[2], operands[1])); else emit_insn (gen_lfiwax (operands[2], operands[1])); @@ -5238,7 +5237,7 @@ (define_insn_and_split "floatunssi operands[1] = rs6000_address_for_fpconvert (operands[1]); if (GET_CODE (operands[2]) == SCRATCH) operands[2] = gen_reg_rtx (DImode); - if (TARGET_VSX_SMALL_INTEGER) + if (TARGET_P8_VECTOR) emit_insn (gen_zero_extendsidi2 (operands[2], operands[1])); else emit_insn (gen_lfiwzx (operands[2], operands[1])); @@ -5423,8 +5422,7 @@ (define_expand "float 4))])] - "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64 - && TARGET_VSX_SMALL_INTEGER" + "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64" { if (MEM_P (operands[1])) operands[1] = rs6000_address_for_fpconvert (operands[1]); @@ -5437,8 +5435,7 @@ (define_insn_and_split "*float (clobber (match_scratch:DI 2 "=wK,wi,wK")) (clobber (match_scratch:DI 3 "=X,r,X")) (clobber (match_scratch: 4 "=X,X,wK"))] - "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64 - && TARGET_VSX_SMALL_INTEGER" + "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64" "#" "&& reload_completed" [(const_int 0)] @@ -5477,8 +5474,7 @@ (define_expand "floatunssi2" "TARGET_HARD_FLOAT && " " { - if (!TARGET_VSX_SMALL_INTEGER) + if (!TARGET_P8_VECTOR) { rtx src = force_reg (mode, operands[1]); @@ -5551,7 +5546,7 @@ (define_insn_and_split "fix_truncs "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && (mode != SFmode || TARGET_SINGLE_FLOAT) && TARGET_STFIWX && can_create_pseudo_p () - && !TARGET_VSX_SMALL_INTEGER" + && !TARGET_P8_VECTOR" "#" "" [(pc)] @@ -5592,7 +5587,7 @@ (define_insn_and_split "fix_truncs (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,"))) (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d")) (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))] - "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_VSX_SMALL_INTEGER" + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_P8_VECTOR" "#" "" [(pc)] @@ -5629,8 +5624,7 @@ (define_expand "fix_trunc 0 "nonimmediate_operand") (fix:QHI (match_operand:SFDF 1 "gpc_reg_operand"))) (clobber (match_scratch:DI 2))])] - "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT - && TARGET_VSX_SMALL_INTEGER" + "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT" { if (MEM_P (operands[0])) operands[0] = rs6000_address_for_fpconvert (operands[0]); @@ -5641,8 +5635,7 @@ (define_insn_and_split "*fix_trunc,"))) (clobber (match_scratch:DI 2 "=X,wi"))] - "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT - && TARGET_VSX_SMALL_INTEGER" + "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT" "#" "&& reload_completed" [(const_int 0)] @@ -5672,7 +5665,7 @@ (define_expand "fixuns_truncsi2" "TARGET_HARD_FLOAT && && TARGET_FCTIWUZ && TARGET_STFIWX" " { - if (!TARGET_VSX_SMALL_INTEGER) + if (!TARGET_P8_VECTOR) { emit_insn (gen_fixuns_truncsi2_stfiwx (operands[0], operands[1])); DONE; @@ -5685,7 +5678,7 @@ (define_insn_and_split "fixuns_trunc && TARGET_FCTIWUZ && TARGET_STFIWX && can_create_pseudo_p () - && !TARGET_VSX_SMALL_INTEGER" + && !TARGET_P8_VECTOR" "#" "" [(pc)] @@ -5734,8 +5727,7 @@ (define_expand "fixuns_trunc< [(parallel [(set (match_operand: 0 "nonimmediate_operand") (unsigned_fix:QHI (match_operand:SFDF 1 "gpc_reg_operand"))) (clobber (match_scratch:DI 2))])] - "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT - && TARGET_VSX_SMALL_INTEGER" + "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT" { if (MEM_P (operands[0])) operands[0] = rs6000_address_for_fpconvert (operands[0]); @@ -5746,8 +5738,7 @@ (define_insn_and_split "*fixuns_trunc,"))) (clobber (match_scratch:DI 2 "=X,wi"))] - "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT - && TARGET_VSX_SMALL_INTEGER" + "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT" "#" "&& reload_completed" [(const_int 0)] @@ -5777,7 +5768,7 @@ (define_insn_and_split "*fixuns_truncz__smallint" [(set (match_operand:SI 0 "vsx_register_operand" "=d,wi") (any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" ",")))] - "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_VSX_SMALL_INTEGER" + "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_P8_VECTOR" "@ fctiwz %0,%1 xscvdpxws %x0,%x1" @@ -5789,7 +5780,7 @@ (define_insn_and_split "*fctiwz_