From patchwork Wed Apr 12 22:45:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 750184 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3w3JtG24fnz9sD5 for ; Thu, 13 Apr 2017 08:45:57 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="iDTiq6WW"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:mime-version:content-type:message-id; q=dns; s= default; b=JaubDiW6JdNpIoMdcAmQBxaUXSrNF6RSjaNchpLnnYHvUDKmHuvy/ 9CnoRIGAUidNaMnBXZxL2p4bwCp/Nshairxe3tGCQ/b6axxMbqcMH0I+2cMpiVAo uJ5ImI33MXVW0qtmg2V5fJF77qsc9b54ywsLSEy8UC1JpsYp2Ywg10= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:mime-version:content-type:message-id; s= default; bh=ZD2P+3ZVD/BqOF/IyFCrGBMvOZI=; b=iDTiq6WW51E3BbFflyAi 8mT6/MzLa3mhuaetpdwxpuX8u4o2qaVI3OczV1ZHshexwmzqO1w56mcpsvtI4HP4 lvqL9vwdRBVBpv4yNkvsS+BbNQgaNf5WasMK5xrI1ZYFK5IkF6g3ALjT3FLprzMQ IDwhCZBk9m3uZj9cYjfegV0= Received: (qmail 81937 invoked by alias); 12 Apr 2017 22:45:47 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 81387 invoked by uid 89); 12 Apr 2017 22:45:40 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-9.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.2 spammy= X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 12 Apr 2017 22:45:39 +0000 Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v3CMhf7e126962 for ; Wed, 12 Apr 2017 18:45:37 -0400 Received: from e34.co.us.ibm.com (e34.co.us.ibm.com [32.97.110.152]) by mx0a-001b2d01.pphosted.com with ESMTP id 29sw2a0fy1-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 12 Apr 2017 18:45:36 -0400 Received: from localhost by e34.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 12 Apr 2017 16:45:32 -0600 Received: from b03ledav003.gho.boulder.ibm.com (b03ledav003.gho.boulder.ibm.com [9.17.130.234]) by b03cxnp07029.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v3CMjVWU15401372; Wed, 12 Apr 2017 15:45:32 -0700 Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 335016A03F; Wed, 12 Apr 2017 16:45:32 -0600 (MDT) Received: from ibm-tiger.the-meissners.org (unknown [9.32.77.111]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP id 1F6386A043; Wed, 12 Apr 2017 16:45:32 -0600 (MDT) Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id 6A17A4A91A; Wed, 12 Apr 2017 18:45:31 -0400 (EDT) Date: Wed, 12 Apr 2017 18:45:31 -0400 From: Michael Meissner To: gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt Subject: [PATCH], Fix PR/target 80099 (internal error with -mno-upper-regs-sf) Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-GCONF: 00 x-cbid: 17041222-0016-0000-0000-0000068C9674 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00006925; HX=3.00000240; KW=3.00000007; PH=3.00000004; SC=3.00000208; SDB=6.00846705; UDB=6.00417668; IPR=6.00625143; BA=6.00005286; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00015026; XFM=3.00000013; UTC=2017-04-12 22:45:34 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17041222-0017-0000-0000-000038EF6A65 Message-Id: <20170412224530.GA29642@ibm-tiger.the-meissners.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-04-12_17:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1704120186 X-IsSubscribed: yes The problem is rs6000_expand_vector_extract did not check for SFmode being allowed in the Altivec (upper) registers, but the insn implementing the variable extract had it as a condition. In looking at the variable extract code, it currently does not require SFmode to go in the Altivec registers, but it does require DImode to go into the Altivec registers (vec_extract of V2DFmode will require DFmode to go in Altivec registers instead of DImode). I have tested this patch on a little endian power8 system and there were no regressions with either bootstrap or make check. [gcc] 2017-04-12 Michael Meissner PR target/80099 * config/rs6000/rs6000.c (rs6000_expand_vector_extract): Make sure that DFmode or DImode as appropriate can go in Altivec registers before generating the faster sequences for variable vec_extracts. * config/rs6000/vsx.md (vsx_extract_v4sf): Remove unneeded TARGET_UPPER_REGS_SF condition. [gcc/testsuite] 2017-04-12 Michael Meissner PR target/80099 * gcc.target/powerpc/pr80099.c: New test. Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 246852) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -7586,15 +7586,23 @@ rs6000_expand_vector_extract (rtx target switch (mode) { case V2DFmode: - emit_insn (gen_vsx_extract_v2df_var (target, vec, elt)); - return; + if (TARGET_UPPER_REGS_DF) + { + emit_insn (gen_vsx_extract_v2df_var (target, vec, elt)); + return; + } + break; case V2DImode: - emit_insn (gen_vsx_extract_v2di_var (target, vec, elt)); - return; + if (TARGET_UPPER_REGS_DI) + { + emit_insn (gen_vsx_extract_v2di_var (target, vec, elt)); + return; + } + break; case V4SFmode: - if (TARGET_UPPER_REGS_SF) + if (TARGET_UPPER_REGS_DI) { emit_insn (gen_vsx_extract_v4sf_var (target, vec, elt)); return; @@ -7602,16 +7610,28 @@ rs6000_expand_vector_extract (rtx target break; case V4SImode: - emit_insn (gen_vsx_extract_v4si_var (target, vec, elt)); - return; + if (TARGET_UPPER_REGS_DI) + { + emit_insn (gen_vsx_extract_v4si_var (target, vec, elt)); + return; + } + break; case V8HImode: - emit_insn (gen_vsx_extract_v8hi_var (target, vec, elt)); - return; + if (TARGET_UPPER_REGS_DI) + { + emit_insn (gen_vsx_extract_v8hi_var (target, vec, elt)); + return; + } + break; case V16QImode: - emit_insn (gen_vsx_extract_v16qi_var (target, vec, elt)); - return; + if (TARGET_UPPER_REGS_DI) + { + emit_insn (gen_vsx_extract_v16qi_var (target, vec, elt)); + return; + } + break; default: gcc_unreachable (); Index: gcc/config/rs6000/vsx.md =================================================================== --- gcc/config/rs6000/vsx.md (revision 246852) +++ gcc/config/rs6000/vsx.md (working copy) @@ -2419,8 +2419,7 @@ (define_insn_and_split "vsx_extract_v4sf UNSPEC_VSX_EXTRACT)) (clobber (match_scratch:DI 3 "=r,&b,&b")) (clobber (match_scratch:V2DI 4 "=&v,X,X"))] - "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT - && TARGET_UPPER_REGS_SF" + "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT" "#" "&& reload_completed" [(const_int 0)] Index: gcc/testsuite/gcc.target/powerpc/pr80099.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/pr80099.c (revision 0) +++ gcc/testsuite/gcc.target/powerpc/pr80099.c (working copy) @@ -0,0 +1,12 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-mcpu=power8 -O2 -mno-upper-regs-di" } */ + +/* PR target/80099: compiler internal error if -mno-upper-regs-di used. */ + +int a; +int int_from_mem (vector float *c) +{ + return __builtin_vec_extract (*c, a); +}