From patchwork Fri Mar 24 14:10:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andreas Krebbel X-Patchwork-Id: 743209 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vqQS04P18z9s8T for ; Sat, 25 Mar 2017 01:15:28 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="nUfIIAFu"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:in-reply-to:references:message-id; q=dns; s= default; b=OGJMlpiwpiZ2XplnvUzPRMP8Tym5C09d9M+vOCy0r597WMIbm9Ug+ 20z2SQ7dh3w46Lt0WkHbGfNEKlwZx0hnn91QTFocP1d5FeRWQnxnN8su/TFw8Vq7 C3Pq+GzoCy4aqWAwc+g1AjTm1vnfSXUOXO3kOP9yMmdLWLicJ782Us= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:in-reply-to:references:message-id; s=default; bh=ZhrCe22NPe5r6bkjG6bFZii3f3Q=; b=nUfIIAFuRNVYlRe4KHOHtuV+YaNL sX1WKKmICTEIzP0Ofq7tUoSr4aBsrdYuuRaOWogdWJ+0TJN7gW+GTXFm+LTcG2jc 42b9bjiDfcPclp/Qeh+BWEGfJe1YKCviQKPcGT6bo9k/A3KS2twFX2MCcQ8Phrz+ SWofdokN+/ZuuyU= Received: (qmail 30182 invoked by alias); 24 Mar 2017 14:11:23 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 28487 invoked by uid 89); 24 Mar 2017 14:11:17 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.2 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.2 spammy=vnn, vnx, 6556, inversion X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 24 Mar 2017 14:11:11 +0000 Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v2OE8dJO115204 for ; Fri, 24 Mar 2017 10:11:10 -0400 Received: from e06smtp11.uk.ibm.com (e06smtp11.uk.ibm.com [195.75.94.107]) by mx0a-001b2d01.pphosted.com with ESMTP id 29cyr5yae9-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Fri, 24 Mar 2017 10:11:10 -0400 Received: from localhost by e06smtp11.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 24 Mar 2017 14:11:05 -0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v2OEB5NK14615024 for ; Fri, 24 Mar 2017 14:11:05 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D4A134C097 for ; Fri, 24 Mar 2017 14:10:43 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BAB114C073 for ; Fri, 24 Mar 2017 14:10:43 +0000 (GMT) Received: from maggie.boeblingen.de.ibm.com (unknown [9.152.212.134]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTPS for ; Fri, 24 Mar 2017 14:10:43 +0000 (GMT) From: Andreas Krebbel To: gcc-patches@gcc.gnu.org Subject: [PATCH 10/16] S/390: arch12: Add support for new vector bit operations. Date: Fri, 24 Mar 2017 15:10:47 +0100 In-Reply-To: <20170324141053.16840-1-krebbel@linux.vnet.ibm.com> References: <20170324141053.16840-1-krebbel@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 17032414-0040-0000-0000-0000036EE975 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17032414-0041-0000-0000-00001F688FA2 Message-Id: <20170324141053.16840-11-krebbel@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-03-24_12:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1703240123 X-IsSubscribed: yes This patch adds support for the new bit operations introduced with arch12. The patch also renames the one complement pattern to the proper RTL standard name. 2017-03-24 Andreas Krebbel * config/s390/s390.c (s390_rtx_costs): Return low costs for the canonical form of ~AND to make sure the new instruction will be used. * config/s390/vector.md ("notand3", "ior_not3") ("notxor3"): Add new pattern definitions. ("*not"): Rename to ... ("one_cmpl2"): ... this. gcc/testsuite/ChangeLog: 2017-03-24 Andreas Krebbel * gcc.target/s390/vxe/bitops-1.c: New test. --- gcc/config/s390/s390.c | 15 ++++++++ gcc/config/s390/vector.md | 31 +++++++++++++++-- gcc/testsuite/ChangeLog | 4 +++ gcc/testsuite/gcc.target/s390/vxe/bitops-1.c | 52 ++++++++++++++++++++++++++++ 4 files changed, 100 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/s390/vxe/bitops-1.c diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index c94edcc..416a15e 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -3373,6 +3373,21 @@ s390_rtx_costs (rtx x, machine_mode mode, int outer_code, *total = COSTS_N_INSNS (2); return true; } + + /* ~AND on a 128 bit mode. This can be done using a vector + instruction. */ + if (TARGET_VXE + && GET_CODE (XEXP (x, 0)) == NOT + && GET_CODE (XEXP (x, 1)) == NOT + && REG_P (XEXP (XEXP (x, 0), 0)) + && REG_P (XEXP (XEXP (x, 1), 0)) + && GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0), 0))) == 16 + && s390_hard_regno_mode_ok (VR0_REGNUM, + GET_MODE (XEXP (XEXP (x, 0), 0)))) + { + *total = COSTS_N_INSNS (1); + return true; + } /* fallthrough */ case ASHIFT: case ASHIFTRT: diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 7ddeb9a..68a8ed0 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -655,6 +655,15 @@ "vn\t%v0,%v1,%v2" [(set_attr "op_type" "VRR")]) +; Vector not and + +(define_insn "notand3" + [(set (match_operand:VT 0 "register_operand" "=v") + (ior:VT (not:VT (match_operand:VT 1 "register_operand" "%v")) + (not:VT (match_operand:VT 2 "register_operand" "v"))))] + "TARGET_VXE" + "vnn\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) ; Vector or @@ -666,6 +675,15 @@ "vo\t%v0,%v1,%v2" [(set_attr "op_type" "VRR")]) +; Vector or with complement + +(define_insn "ior_not3" + [(set (match_operand:VT 0 "register_operand" "=v") + (ior:VT (not:VT (match_operand:VT 2 "register_operand" "v")) + (match_operand:VT 1 "register_operand" "%v")))] + "TARGET_VXE" + "voc\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) ; Vector xor @@ -677,9 +695,18 @@ "vx\t%v0,%v1,%v2" [(set_attr "op_type" "VRR")]) +; Vector not xor + +(define_insn "notxor3" + [(set (match_operand:VT 0 "register_operand" "=v") + (not:VT (xor:VT (match_operand:VT 1 "register_operand" "%v") + (match_operand:VT 2 "register_operand" "v"))))] + "TARGET_VXE" + "vnx\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) -; Bitwise inversion of a vector - used for vec_cmpne -(define_insn "*not" +; Bitwise inversion of a vector +(define_insn "one_cmpl2" [(set (match_operand:VT 0 "register_operand" "=v") (not:VT (match_operand:VT 1 "register_operand" "v")))] "TARGET_VX" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9ca13ab..bbdd3c8 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,9 @@ 2017-03-24 Andreas Krebbel + * gcc.target/s390/vxe/bitops-1.c: New test. + +2017-03-24 Andreas Krebbel + * gcc.target/s390/s390.exp: Run tests in arch12 and vxe dirs. * lib/target-supports.exp: Add effective target check s390_vxe. diff --git a/gcc/testsuite/gcc.target/s390/vxe/bitops-1.c b/gcc/testsuite/gcc.target/s390/vxe/bitops-1.c new file mode 100644 index 0000000..bdf7457 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vxe/bitops-1.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -mzarch -march=arch12 --save-temps" } */ +/* { dg-require-effective-target s390_vxe } */ + +typedef unsigned int uv4si __attribute__((vector_size(16))); + +uv4si __attribute__((noinline)) +not_xor (uv4si a, uv4si b) +{ + return ~(a ^ b); +} +/* { dg-final { scan-assembler-times "vnx\t%v24,%v24,%v26" 1 } } */ + +uv4si __attribute__((noinline)) +not_and (uv4si a, uv4si b) +{ + return ~(a & b); +} +/* { dg-final { scan-assembler-times "vnn\t%v24,%v24,%v26" 1 } } */ + +uv4si __attribute__((noinline)) +or_not (uv4si a, uv4si b) +{ + return a | ~b; +} +/* { dg-final { scan-assembler-times "voc\t%v24,%v24,%v26" 1 } } */ + + +int +main () +{ + uv4si a = (uv4si){ 42, 1, 0, 2 }; + uv4si b = (uv4si){ 42, 2, 0, 2 }; + uv4si c; + + c = not_xor (a, b); + + if (c[0] != ~0 || c[1] != ~3 || c[2] != ~0 || c[3] != ~0) + __builtin_abort (); + + c = not_and (a, b); + + if (c[0] != ~42 || c[1] != ~0 || c[2] != ~0 || c[3] != ~2) + __builtin_abort (); + + c = or_not (a, b); + + if (c[0] != ~0 || c[1] != ~2 || c[2] != ~0 || c[3] != ~0) + __builtin_abort (); + + return 0; +}