From patchwork Fri Mar 17 22:52:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 740548 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vlLM44m66z9rvt for ; Sat, 18 Mar 2017 09:57:04 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="LoSFLeid"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=cPiS5QVv8fMJ Yfh/6uzwGQp/+BOD6Kz6O5ysaWz1hTWJTcJ3Fzb22ltMpcT2dG/Tr83JCJZk03ON ssFUNwF8Xkl7RWXfLzL0t8wvURTOU1UStPIJ2jVmsZlXXbfTWHVuYgUGPwiL98cN F2pLV8slvsLqPEJt8TsbmV+zCjPB/cw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=t7ps9so5dWCnrrVvIO K2ev4Mhfk=; b=LoSFLeidGUKmEt7zWoHhkyI9vMGKXX9BUbGll4c84lrLiC0VRC 0qrNibawHGL0h2wNfqAOwGLwWYLnc9k/VMeMipyAKUJa6ZxbC8eZPEc9XnAkGxBJ JxEbb+nAqGABZ2HxGjAfJe86N/fO3i9WhbJ/SbyrCtkizZgfghuYlj5os= Received: (qmail 81657 invoked by alias); 17 Mar 2017 22:56:44 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 81550 invoked by uid 89); 17 Mar 2017 22:56:43 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.1 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy=formally, Hx-languages-length:1951, letter X-HELO: mail-pg0-f68.google.com Received: from mail-pg0-f68.google.com (HELO mail-pg0-f68.google.com) (74.125.83.68) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 17 Mar 2017 22:56:42 +0000 Received: by mail-pg0-f68.google.com with SMTP id b5so11756415pgg.1 for ; Fri, 17 Mar 2017 15:56:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=L+vO5/tHBy55v6JRbpXhq1T9PJRkcGd+qXgpXT2tI0I=; b=HZIS9u8Zilr0DoBYoVJT/4ENRGfNB51DvT9WdBkESG9Ogjo6KSzySlcAFR33d+oUOT 2hYZMeUj6r83OvUvfu6M4rRF0NOdbpQmaE/rm1Alff9nZ+4s0lzmx8yGD5sErZXio0zc BHgYitkoYC0ftQqJHXJp7v4SEbHPj70Dq83UahWzdqtMfbF1gjRlJakH8SYIOlCqVF9l OwKq8D6YWqQB6iLSzXmfYmCLQyICK6srLHP430fOWrWhizloMEmmyAxhi32i1uVLf/2T qOvxiejQYkEbjZrOfL+teLkc1QvellJtjK7rpGdU+GOuNEZ3eyAJKP6DHz8d31jYtRQC fKOQ== X-Gm-Message-State: AFeK/H2+r3dc/fCBqC98TPGKr4M6DYjSg+3f96lhxbCiQopHJGDTfi4Jmb9AYnHTjbngyg== X-Received: by 10.84.199.170 with SMTP id r39mr22852010pld.144.1489791401875; Fri, 17 Mar 2017 15:56:41 -0700 (PDT) Received: from localhost ([216.38.154.21]) by smtp.gmail.com with ESMTPSA id d2sm18878456pgf.35.2017.03.17.15.56.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Mar 2017 15:56:41 -0700 (PDT) From: Palmer Dabbelt To: gcc-patches@gcc.gnu.org Cc: Palmer Dabbelt Subject: [PATCH] Use more conservative fences on RISC-V Date: Fri, 17 Mar 2017 15:52:54 -0700 Message-Id: <20170317225254.19182-1-palmer@dabbelt.com> X-IsSubscribed: yes The RISC-V memory model is still in the process of being formally specified, so for now we're going to be safe and add the I/O bits to userspace fences because there's no way to know if userspace is touching memory-mapped I/O regions at compile time. This will have no impact on existing microarchitecutres because they treat all fences conservatively. gcc/ChangeLog: 2017-03-17 Palmer Dabbelt * config/riscv/riscv.c (riscv_print_operand): Use "fence iorw,ow". * config/riscv/sync.mc (mem_thread_fence_1): Use "fence iorw,iorw". --- gcc/ChangeLog | 7 +++++++ gcc/config/riscv/riscv.c | 2 +- gcc/config/riscv/sync.md | 2 +- 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3e108dd..de32689 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-03-17 Palmer Dabbelt + + * config/riscv/riscv.c (riscv_print_operand): Use "fence + iorw,ow". + * config/riscv/sync.mc (mem_thread_fence_1): Use "fence + iorw,iorw". + 2017-03-17 Palmer Dabbelt : Add riscv32-*-elf, diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 25cc803..fa93c3c 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -2794,7 +2794,7 @@ riscv_print_operand (FILE *file, rtx op, int letter) case 'F': if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op))) - fputs ("fence rw,w; ", file); + fputs ("fence iorw,ow; ", file); break; default: diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 09970b9..cde19e3 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -53,7 +53,7 @@ (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) (match_operand:SI 1 "const_int_operand" "")] ;; model "" - "fence\trw,rw") + "fence\tiorw,iorw") ;; Atomic memory operations.