From patchwork Fri Mar 3 18:10:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 735200 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vZcg72qfKz9ryQ for ; Sat, 4 Mar 2017 05:10:42 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="ILJ6b/EN"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:mime-version:content-type:message-id; q=dns; s= default; b=jUVn8vTR9O/9EOd0tJ6p8bbOCjAoBH+f+28oQNYy01adInEDthNuz sIKXYIA/LbiJDoawTggmHFFRK1PqrYVmsVbe9bdK6pxE+GJ3N8M17RbkWpUm5IYQ 0a7WaMHkeS4Pw/zWKtbOlNLHFIsdj2GYrf8iCs7tupsYvdwy4FPLx8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:mime-version:content-type:message-id; s= default; bh=ZFLjMr3OGDIj2WEb+/TA2APuoJY=; b=ILJ6b/ENdSCIPahIs0F5 X4KyWTB3AD/vO2Q8BKdc3AaV9DRi1Nie0oewZ7fPURjeYtzuJG/It4lHjl3GfBCe ws4ebBh23qG4N92suUuRkv+fW+7hav2kqEw/hZRc5817GAgxbmqc6IMd5gp/fQCe U4CvoSQG2BwQhDre39ovQXY= Received: (qmail 8920 invoked by alias); 3 Mar 2017 18:10:32 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 8910 invoked by uid 89); 3 Mar 2017 18:10:31 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-9.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, KAM_LAZY_DOMAIN_SECURITY, KHOP_DYNAMIC, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.2 spammy=31st, di2, king, U*meissner X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 03 Mar 2017 18:10:29 +0000 Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v23I9NH6002281 for ; Fri, 3 Mar 2017 13:10:28 -0500 Received: from e19.ny.us.ibm.com (e19.ny.us.ibm.com [129.33.205.209]) by mx0a-001b2d01.pphosted.com with ESMTP id 28xs8evcgx-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Fri, 03 Mar 2017 13:10:28 -0500 Received: from localhost by e19.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 3 Mar 2017 13:10:24 -0500 Received: from b01cxnp23034.gho.pok.ibm.com (b01cxnp23034.gho.pok.ibm.com [9.57.198.29]) by d01dlp03.pok.ibm.com (Postfix) with ESMTP id 6EC51C90041; Fri, 3 Mar 2017 13:10:04 -0500 (EST) Received: from b01ledav006.gho.pok.ibm.com (b01ledav006.gho.pok.ibm.com [9.57.199.111]) by b01cxnp23034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v23IAOTG45285462; Fri, 3 Mar 2017 18:10:24 GMT Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8051CAC043; Fri, 3 Mar 2017 13:10:19 -0500 (EST) Received: from ibm-tiger.the-meissners.org (unknown [9.32.77.111]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTP id 64D25AC03F; Fri, 3 Mar 2017 13:10:19 -0500 (EST) Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id F2D86481FE; Fri, 3 Mar 2017 13:10:20 -0500 (EST) Date: Fri, 3 Mar 2017 13:10:18 -0500 From: Michael Meissner To: gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt Subject: [PATCH], PR target/79038, Improve char/short -> _Float128 conversions Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-GCONF: 00 X-Content-Scanned: Fidelis XPS MAILER x-cbid: 17030318-0056-0000-0000-000002ECD4B6 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00006716; HX=3.00000240; KW=3.00000007; PH=3.00000004; SC=3.00000206; SDB=6.00829621; UDB=6.00406746; IPR=6.00607119; BA=6.00005186; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00014512; XFM=3.00000012; UTC=2017-03-03 18:10:25 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17030318-0057-0000-0000-00000722DA21 Message-Id: <20170303181018.GA18208@ibm-tiger.the-meissners.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-03-03_12:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1703030164 X-IsSubscribed: yes On January 31st I commited a patch that improves conversion of signed/unsigned char/short values to 32-bit and 64-bit floating point on Power9, particularly when the values are coming from memory. This adds similar support to _Float128/__float128 (i.e. IEEE 128-bit floating point). I have tested this patch via bootstrap and make check and there were no regressions. Can I check this patch into the trunk? [gcc] 2017-03-03 Michael Meissner PR target/79038 * config/rs6000/rs6000.md (float2): Define insns to convert from signed/unsigned char/short to IEEE 128-bit floating point. (floatuns2): Likewise. [gcc/testsuite] 2017-02-24 Michael Meissner PR target/79038 * gcc.target/powerpc/pr79038-1.c: New test. Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 245815) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -14467,6 +14467,43 @@ (define_insn_and_split "float_si2_ operands[2] = gen_reg_rtx (DImode); }) +(define_insn_and_split "float2" + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v,v,v") + (float:IEEE128 (match_operand:QHI 1 "nonimmediate_operand" "v,r,Z"))) + (clobber (match_scratch:DI 2 "=X,r,X"))] + "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "#" + "&& reload_completed" + [(const_int 0)] +{ + rtx dest = operands[0]; + rtx src = operands[1]; + rtx dest_di = gen_rtx_REG (DImode, REGNO (dest)); + + if (altivec_register_operand (src, mode)) + emit_insn (gen_extenddi2 (dest_di, src)); + else if (int_reg_operand (src, mode)) + { + rtx ext_di = operands[2]; + emit_insn (gen_extenddi2 (ext_di, src)); + emit_move_insn (dest_di, ext_di); + } + else if (MEM_P (src)) + { + rtx dest_qhi = gen_rtx_REG (mode, REGNO (dest)); + emit_move_insn (dest_qhi, src); + emit_insn (gen_extenddi2 (dest_di, dest_qhi)); + } + else + gcc_unreachable (); + + emit_insn (gen_float_di2_hw (dest, dest_di)); + DONE; +} + [(set_attr "length" "8,12,12") + (set_attr "type" "vecfloat") + (set_attr "size" "128")]) + (define_insn "floatuns_di2_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unsigned_float:IEEE128 @@ -14493,6 +14530,38 @@ (define_insn_and_split "floatuns_s operands[2] = gen_reg_rtx (DImode); }) +(define_insn_and_split "floatuns2" + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v,v,v") + (unsigned_float:IEEE128 + (match_operand:QHI 1 "nonimmediate_operand" "v,r,Z"))) + (clobber (match_scratch:DI 2 "=X,r,X"))] + "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "#" + "&& reload_completed" + [(const_int 0)] +{ + rtx dest = operands[0]; + rtx src = operands[1]; + rtx dest_di = gen_rtx_REG (DImode, REGNO (dest)); + + if (altivec_register_operand (src, mode) || MEM_P (src)) + emit_insn (gen_zero_extenddi2 (dest_di, src)); + else if (int_reg_operand (src, mode)) + { + rtx ext_di = operands[2]; + emit_insn (gen_zero_extenddi2 (ext_di, src)); + emit_move_insn (dest_di, ext_di); + } + else + gcc_unreachable (); + + emit_insn (gen_floatuns_di2_hw (dest, dest_di)); + DONE; +} + [(set_attr "length" "8,12,8") + (set_attr "type" "vecfloat") + (set_attr "size" "128")]) + ;; IEEE 128-bit instructions with round to odd semantics (define_insn "*truncdf2_odd" [(set (match_operand:DF 0 "vsx_register_operand" "=v") Index: gcc/testsuite/gcc.target/powerpc/pr79038-1.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/pr79038-1.c (revision 0) +++ gcc/testsuite/gcc.target/powerpc/pr79038-1.c (revision 0) @@ -0,0 +1,39 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2 -mfloat128" } */ + +#ifndef TYPE +#define TYPE _Float128 +#endif + +TYPE +return_convert_uchar_to_float128_mem (unsigned char *p_uc) +{ + return (TYPE) p_uc[10]; +} + +TYPE +return_convert_schar_to_float128_mem (signed char *p_sc) +{ + return (TYPE) p_sc[10]; +} + +TYPE +return_convert_ushort_to_float128_mem (unsigned short *p_us) +{ + return (TYPE) p_us[10]; +} + +TYPE +return_convert_sshort_to_float128_mem (short *p_ss) +{ + return (TYPE) p_ss[10]; +} + +/* { dg-final { scan-assembler {\mlxsi[bh]zx\M} } } */ +/* { dg-final { scan-assembler {\mvexts[bh]2d\M} } } */ +/* { dg-final { scan-assembler-not {\mextsb\M} } } */ +/* { dg-final { scan-assembler-not {\ml[bh][az]\M} } } */ +/* { dg-final { scan-assembler-not {\mmtvsrw[az]\M} } } */ +