diff mbox

, Fix PR target/79179, wrong constraint for power9

Message ID 20170126010303.GA20850@ibm-tiger.the-meissners.org
State New
Headers show

Commit Message

Michael Meissner Jan. 26, 2017, 1:03 a.m. UTC
This patch fixes the wrong constraint (o instead of wY) for a STXSD instruction
on a vector extract operation that is optimizd to do a store if the element
being extracted is in the right position.

I have built a compiler with/with out the patch on a little endian power8
system.  The runs finished with no regressions.  Can I check it into trunk?

[gcc]
2017-01-25  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/79179
	* config/rs6000/vsx.md (vsx_extract_<mode>_store): Use wY
	constraint instead of o for the stxsd instruction.

[gcc/testsuite]
2017-01-25  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/79179
	* gcc.target/powerpc/pr79179.c: New test.

Comments

Segher Boessenkool Jan. 26, 2017, 2:48 a.m. UTC | #1
On Wed, Jan 25, 2017 at 08:03:04PM -0500, Michael Meissner wrote:
> This patch fixes the wrong constraint (o instead of wY) for a STXSD instruction
> on a vector extract operation that is optimizd to do a store if the element
> being extracted is in the right position.
> 
> I have built a compiler with/with out the patch on a little endian power8
> system.  The runs finished with no regressions.  Can I check it into trunk?

Yes please.  Thanks,


Segher


> 2017-01-25  Michael Meissner  <meissner@linux.vnet.ibm.com>
> 
> 	PR target/79179
> 	* config/rs6000/vsx.md (vsx_extract_<mode>_store): Use wY
> 	constraint instead of o for the stxsd instruction.
> 
> [gcc/testsuite]
> 2017-01-25  Michael Meissner  <meissner@linux.vnet.ibm.com>
> 
> 	PR target/79179
> 	* gcc.target/powerpc/pr79179.c: New test.
diff mbox

Patch

Index: gcc/config/rs6000/vsx.md
===================================================================
--- gcc/config/rs6000/vsx.md	(revision 244906)
+++ gcc/config/rs6000/vsx.md	(working copy)
@@ -2323,7 +2323,7 @@  (define_insn_and_split "*vsx_extract_<P:
 ;; Optimize storing a single scalar element that is the right location to
 ;; memory
 (define_insn "*vsx_extract_<mode>_store"
-  [(set (match_operand:<VS_scalar> 0 "memory_operand" "=m,Z,o")
+  [(set (match_operand:<VS_scalar> 0 "memory_operand" "=m,Z,wY")
 	(vec_select:<VS_scalar>
 	 (match_operand:VSX_D 1 "register_operand" "d,wv,wb")
 	 (parallel [(match_operand:QI 2 "vsx_scalar_64bit" "wD,wD,wD")])))]
Index: gcc/testsuite/gcc.target/powerpc/pr79179.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr79179.c	(revision 0)
+++ gcc/testsuite/gcc.target/powerpc/pr79179.c	(revision 0)
@@ -0,0 +1,23 @@ 
+/* { dg-do assemble { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mcpu=power9 -O3" } */
+
+/* Compile with -O3 -mcpu=power9.  It originally generated
+
+        stxsd 12,1(9)
+
+   which is illegal.  */
+
+#pragma pack(1)
+struct {
+        signed : 1;
+        unsigned long a;
+} b;
+
+void c(void)
+{
+        b.a = 0;
+        for (; b.a <= 45; b.a = (long)b.a + 1)
+                ;
+}