From patchwork Tue Jan 3 21:43:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 710707 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ttSBq4JQLz9sQw for ; Wed, 4 Jan 2017 08:44:15 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="Nn2AAgKY"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:mime-version:content-type:message-id; q=dns; s= default; b=ga00sg2j9rAK8XpVDh2vj/oYY+6HloXsOEBHqwc5WB4ZwXs+a9faF vGAJepPQyc/WFYMP5vLZVeRDuqgB6BUfMMSE0EJehL302XET6avRD4XK1VLHOYVy 4Qztbmdju+t2dNSExQZgUewEpecDCT2/FG7V2v0fjxiDOTnLgvCzYg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:mime-version:content-type:message-id; s= default; bh=GVnxeYyhX/pJzqbk92KADjb0gvE=; b=Nn2AAgKYuHyAxfKWkLib kHc82HPzO1tILSSsOtaWe71MN/psBM2yairvVZoQelA7GHSHJg+Cy7NWO9uiATIe ftjhIBOS4uXyw8TVOc/xq58iSC+safCBXK4OPLz4x2QhnCitw4WuX6Ppml/uMnM0 36yYoMVF0WZTuqzFhEaGnuw= Received: (qmail 16617 invoked by alias); 3 Jan 2017 21:44:07 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 16605 invoked by uid 89); 3 Jan 2017 21:44:07 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.7 required=5.0 tests=AWL, BAYES_00, KAM_ASCII_DIVIDERS, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_LOW autolearn=no version=3.3.2 spammy=King, zm, deposited, altivec.h X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 03 Jan 2017 21:43:57 +0000 Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id v03Lcmc4087943 for ; Tue, 3 Jan 2017 16:43:55 -0500 Received: from e18.ny.us.ibm.com (e18.ny.us.ibm.com [129.33.205.208]) by mx0a-001b2d01.pphosted.com with ESMTP id 27rdf7shab-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Tue, 03 Jan 2017 16:43:55 -0500 Received: from localhost by e18.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 3 Jan 2017 16:43:52 -0500 Received: from b01cxnp22034.gho.pok.ibm.com (b01cxnp22034.gho.pok.ibm.com [9.57.198.24]) by d01dlp03.pok.ibm.com (Postfix) with ESMTP id 213A9C90043; Tue, 3 Jan 2017 16:43:35 -0500 (EST) Received: from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com [9.57.199.107]) by b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v03LhqtD42991676; Tue, 3 Jan 2017 21:43:52 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EA7AA124035; Tue, 3 Jan 2017 16:43:51 -0500 (EST) Received: from ibm-tiger.the-meissners.org (unknown [9.32.77.111]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTP id D00CB124037; Tue, 3 Jan 2017 16:43:51 -0500 (EST) Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id D7EC247340; Tue, 3 Jan 2017 16:43:50 -0500 (EST) Date: Tue, 3 Jan 2017 16:43:49 -0500 From: Michael Meissner To: gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt Subject: [PATCH], PR tqrget/78953, Fix power9 insn does not meet its constraints Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-GCONF: 00 X-Content-Scanned: Fidelis XPS MAILER x-cbid: 17010321-0044-0000-0000-0000022E4ECD X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00006368; HX=3.00000240; KW=3.00000007; PH=3.00000004; SC=3.00000199; SDB=6.00803094; UDB=6.00390657; IPR=6.00580945; BA=6.00005028; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00013813; XFM=3.00000011; UTC=2017-01-03 21:43:53 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17010321-0045-0000-0000-0000065B4ECE Message-Id: <20170103214349.GA32146@ibm-tiger.the-meissners.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-01-03_18:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1701030329 X-IsSubscribed: yes In builting Spec 2006 with -mcpu=power9 with -O3, two of the benchmarks (gamess and calculix) did not build due to an "insn does not match its constraints" error. (insn 2674 2673 2675 37 (parallel [ (set (reg:SI 0 0 [985]) (vec_select:SI (reg:V4SI 32 0 [orig:378 vect__50.42 ] [378]) (parallel [ (const_int 1 [0x1]) ]))) (clobber (reg:SI 31 31 [986])) ]) "SPOOLES/MSMD/src/MSMD_init.c":113 1184 {vsx_extract_v4si_p9} (expr_list:REG_UNUSED (reg:SI 31 31 [986]) (nil))) This insn was formed by vsx_extract_v4si_store_p9 splitting the following insn after register allocation: (insn 376 374 378 32 (parallel [ (set (mem:SI (plus:DI (reg:DI 7 7 [orig:394 ivtmp.316 ] [394]) (const_int 112 [0x70])) [3 MEM[base: _399, offset: 112B]+0 S4 A32]) (vec_select:SI (reg:V4SI 32 0 [orig:355 vect__50.286 ] [355]) (parallel [ (const_int 2 [0x2]) ]))) (clobber (reg:SI 9 9 [675])) (clobber (reg:SI 10 10 [676])) ]) "SPOOLES/MSMD/src/MSMD_init.c":113 1191 {*vsx_extract_v4si_store_p9} (nil)) It split it to: (insn 968 381 969 32 (parallel [ (set (reg:SI 44 12 [671]) (vec_select:SI (reg:V4SI 32 0 [orig:355 vect__50.286 ] [355]) (parallel [ (const_int 0 [0]) ]))) (clobber (scratch:SI)) ]) "SPOOLES/MSMD/src/MSMD_init.c":113 1185 {vsx_extract_v4si_p9} (nil)) Unfortunately, when it is splitting a word extract to be deposited into a GPR register, it needs to use a traditional Altivec register. The following patch fixes this: [gcc] 2017-01-03 Michael Meissner PR target/78953 * config/rs6000/vsx.md (vsx_extract__store_p9): If we are extracting SImode to a GPR register so that we can generate a store, limit the vector to be in a traditional Altivec register for the vextuwrx instruction. [gcc/testsuite] 2017-01-03 Michael Meissner PR target/78953 * gcc.target/powerpc/pr78953.c: New test. I did the usual bootstrap and make check with no regression on a little endinan power8 system. I also compiled the two Spec 2006 benchmarks that failed and they now build. Is this ok for the trunk? It does not need to be applied to GCC 6.x since the word extract optimization is new to GCC 7. Index: gcc/config/rs6000/vsx.md =================================================================== --- gcc/config/rs6000/vsx.md (revision 243966) +++ gcc/config/rs6000/vsx.md (working copy) @@ -2628,7 +2628,7 @@ (define_insn_and_split "*vsx_extract__store_p9" [(set (match_operand: 0 "memory_operand" "=Z,m") (vec_select: - (match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" ",") + (match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" ",v") (parallel [(match_operand:QI 2 "const_int_operand" "n,n")]))) (clobber (match_scratch: 3 "=,&r")) (clobber (match_scratch:SI 4 "=X,&r"))] Index: gcc/testsuite/gcc.target/powerpc/pr78953.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/pr78953.c (revision 0) +++ gcc/testsuite/gcc.target/powerpc/pr78953.c (working copy) @@ -0,0 +1,19 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */ + +#include + +/* PR 78953: mem = vec_extract (V4SI, ) failed if the vector was in a + traditional FPR register. */ + +void +foo (vector int *vp, int *ip) +{ + vector int v = *vp; + __asm__ (" # fpr %x0" : "+d" (v)); + ip[4] = vec_extract (v, 0); +} + +/* { dg-final { scan-assembler "xxextractuw\|vextuw\[lr\]x" } } */