From patchwork Tue Sep 20 23:38:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 672493 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3sdzjp2jwdz9sCg for ; Wed, 21 Sep 2016 09:39:08 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=ecmt2qtx; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:mime-version:content-type:message-id; q=dns; s= default; b=j8fB/t+mLFmXO4D1bQWuYKa/nVIGgvY9UTlcJtlnraHduLI8ydFXz truuQGlNVNhrAMrrxL4Senyl3a9Tj285U6/LVk+E8OoMbju3xxEk5IuNVfFP8WX+ tGMc8yfNyzIjflIHvRL6i4ZbU1yk6FYzZGP8V39bOPYARaooFt94P4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:mime-version:content-type:message-id; s= default; bh=F96pHIpKWbondJ1604abzTUFB3o=; b=ecmt2qtxK0pBVIstQbpd /wLVR2IIK5KXvbT+1fFeoEwXoCIQBl7i+NpgMlJ8ldODttIis2Ja1+4+ldiHpu5Z aVUT59R/yTJPH7TnN7GTmkT+VA99ZEnD/mliYihdGqgJOP1CZjp7jAm8PQd66xVc v6evgB1/MgJ8mNGCczzx7KQ= Received: (qmail 25869 invoked by alias); 20 Sep 2016 23:39:00 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 25844 invoked by uid 89); 20 Sep 2016 23:38:59 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=1.1 required=5.0 tests=AWL, BAYES_40, KAM_ASCII_DIVIDERS, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_LOW autolearn=no version=3.3.2 spammy=978, 2506r, meissnerlinuxvnetibmcom, 8994797 X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 20 Sep 2016 23:38:49 +0000 Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id u8KNcPqf068268 for ; Tue, 20 Sep 2016 19:38:47 -0400 Received: from e17.ny.us.ibm.com (e17.ny.us.ibm.com [129.33.205.207]) by mx0b-001b2d01.pphosted.com with ESMTP id 25jmr1fhrc-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Tue, 20 Sep 2016 19:38:47 -0400 Received: from localhost by e17.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 20 Sep 2016 19:38:45 -0400 Received: from b01cxnp23032.gho.pok.ibm.com (b01cxnp23032.gho.pok.ibm.com [9.57.198.27]) by d01dlp03.pok.ibm.com (Postfix) with ESMTP id 832D5C90042; Tue, 20 Sep 2016 19:38:31 -0400 (EDT) Received: from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com [9.57.199.107]) by b01cxnp23032.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u8KNcn2A15597906; Tue, 20 Sep 2016 23:38:49 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6E86A124037; Tue, 20 Sep 2016 19:38:44 -0400 (EDT) Received: from ibm-tiger.the-meissners.org (unknown [9.32.77.111]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTP id 527A6124035; Tue, 20 Sep 2016 19:38:44 -0400 (EDT) Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id B408D44B70; Tue, 20 Sep 2016 19:38:43 -0400 (EDT) Date: Tue, 20 Sep 2016 19:38:43 -0400 From: Michael Meissner To: gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt Subject: [PATCH], PR 77670, Fix PowerPC ISA 3.0 -mpower9-minmax code generation Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-GCONF: 00 X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16092023-0040-0000-0000-00000163FE41 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00005793; HX=3.00000240; KW=3.00000007; PH=3.00000004; SC=3.00000185; SDB=6.00759648; UDB=6.00361156; IPR=6.00534004; BA=6.00004739; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00012732; XFM=3.00000011; UTC=2016-09-20 23:38:46 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 16092023-0041-0000-0000-000005570532 Message-Id: <20160920233843.GA31065@ibm-tiger.the-meissners.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-09-20_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1609020000 definitions=main-1609200313 X-IsSubscribed: yes There are some instructions in PowerPC ISA 3.0 that are not currently enabled by default when you use -mcpu=power9. These instructions are currently added with the -mpower9-minmax switch. I recently built Spec 2006 with the current trunk compiler, and I discovered that three of the benchmarks (gamess, povray, and soplex) do not build when you use the -mpower9-minmiax option. In particular, ISA 3.0 adds 3 new instructions: XSCMPEQDP, XSCMPGEDP, and XSCMPGTDP that are similar to the vector instructions in that they set the scalar part of the vector register to all 0's or all 1's so that the XXSEL instruction can be used to do a floating point conditional move. The code did not provide an inverted operation that moves the registers if the condition is false instead of true. I added the an insn splitter for the inverted operation to fix the problem. In testing it, I discovered that when I implemented the XXSEL operation for scalar, I had the registers backwards. I provided a fix for this as well. I rebuilt Spec 2016, and it all builds now. I also tested a small program on the simulator and it generated the correct output. Since this is in ISA 3.0 code only, I did not do the full bootstrap and make check sequence. I can do this if you prefer. Is the patch ok to put into the trunk? 2016-09-20 Michael Meissner PR target/77670 * config/rs6000/predicates.md (invert_fpmask_comparison_operator): New predicate that matches the ISA 3.0 XSCMP{EQ,GT,GE}DP instructions when you want to invert the test. * config/rs6000/rs6000.md (fpmask): Use the arguments in the correct order for XXSEL. (movcc_invert_p9): Define the inverted test for using XSCMP{EQ,GT,GE}DP. Index: gcc/config/rs6000/predicates.md =================================================================== --- gcc/config/rs6000/predicates.md (revision 240283) +++ gcc/config/rs6000/predicates.md (working copy) @@ -1172,6 +1172,12 @@ (define_predicate "scc_rev_comparison_op (define_predicate "fpmask_comparison_operator" (match_code "eq,gt,ge")) +;; Return 1 if OP is a comparison operator suitable for vector/scalar +;; comparisons that generate a 0/-1 mask (i.e. the inverse of +;; fpmask_comparison_operator). +(define_predicate "invert_fpmask_comparison_operator" + (match_code "ne,unlt,unle")) + ;; Return 1 if OP is a comparison operation that is valid for a branch ;; insn, which is true if the corresponding bit in the CC register is set. (define_predicate "branch_positive_comparison_operator" Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 240283) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -4882,6 +4882,43 @@ (define_insn_and_split "*mov< [(set_attr "length" "8") (set_attr "type" "vecperm")]) +;; Handle inverting the fpmask comparisons. +(define_insn_and_split "*movcc_invert_p9" + [(set (match_operand:SFDF 0 "vsx_register_operand" "=&,") + (if_then_else:SFDF + (match_operator:CCFP 1 "invert_fpmask_comparison_operator" + [(match_operand:SFDF2 2 "vsx_register_operand" ",") + (match_operand:SFDF2 3 "vsx_register_operand" ",")]) + (match_operand:SFDF 4 "vsx_register_operand" ",") + (match_operand:SFDF 5 "vsx_register_operand" ","))) + (clobber (match_scratch:V2DI 6 "=0,&wa"))] + "TARGET_P9_MINMAX" + "#" + "" + [(set (match_dup 6) + (if_then_else:V2DI (match_dup 9) + (match_dup 7) + (match_dup 8))) + (set (match_dup 0) + (if_then_else:SFDF (ne (match_dup 6) + (match_dup 8)) + (match_dup 5) + (match_dup 4)))] +{ + rtx op1 = operands[1]; + enum rtx_code cond = reverse_condition_maybe_unordered (GET_CODE (op1)); + + if (GET_CODE (operands[6]) == SCRATCH) + operands[6] = gen_reg_rtx (V2DImode); + + operands[7] = CONSTM1_RTX (V2DImode); + operands[8] = CONST0_RTX (V2DImode); + + operands[9] = gen_rtx_fmt_ee (cond, CCFPmode, operands[2], operands[3]); +} + [(set_attr "length" "8") + (set_attr "type" "vecperm")]) + (define_insn "*fpmask" [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") (if_then_else:V2DI @@ -4901,7 +4938,7 @@ (define_insn "*xxsel" (match_operand:SFDF 3 "vsx_register_operand" "") (match_operand:SFDF 4 "vsx_register_operand" "")))] "TARGET_P9_MINMAX" - "xxsel %x0,%x1,%x3,%x4" + "xxsel %x0,%x4,%x3,%x1" [(set_attr "type" "vecmove")])