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[58.160.146.233]) by smtp.gmail.com with ESMTPSA id sk4sm5469005pac.16.2016.08.02.07.35.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Aug 2016 07:35:10 -0700 (PDT) Received: by bubble.grove.modra.org (Postfix, from userid 1000) id 1DBEFC1986; Wed, 3 Aug 2016 00:05:07 +0930 (ACST) Date: Wed, 3 Aug 2016 00:05:07 +0930 From: Alan Modra To: gcc-patches@gcc.gnu.org Cc: Segher Boessenkool Subject: [RS6000] cost SLOW_UNALIGNED_ACCESS Message-ID: <20160802143506.GG20904@bubble.grove.modra.org> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.24 (2015-08-30) X-IsSubscribed: yes As noted in the last patch, rs6000_rtx_costs ought to cost slow unaligned mems. This stops combine merging loads/stores with a mode-changing SET subreg, if the load/store in the subreg mode would be slow. Costing slow mems at 100 insns is just an order of magnitude estimate. (The alignment interrupt does cost quite a lot. Experiments on power8 with a misaligned lwarx showed taking the alignment interrupt cost roughly 300 insns.) Boostrapped and regression tested powerpc64le-linux and powerpc64-linux. * config/rs6000/rs6000.c (rs6000_rtx_costs): Make unaligned mem cost more. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 5b9aae2..2ae3e7e 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -34336,11 +34336,16 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code, case CONST: case HIGH: case SYMBOL_REF: + *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2); + return true; + case MEM: /* When optimizing for size, MEM should be slightly more expensive than generating address, e.g., (plus (reg) (const)). L1 cache latency is about two instructions. */ *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2); + if (SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (x))) + *total += COSTS_N_INSNS (100); return true; case LABEL_REF: