From 5136f74f61dc3df0229d43d5f13017280838a011 Mon Sep 17 00:00:00 2001
From: Dominik Vogt <vogt@linux.vnet.ibm.com>
Date: Wed, 25 May 2016 11:47:00 +0100
Subject: [PATCH] S/390: Add support for z13 instructions lochi and locghi.

---
 gcc/config/s390/predicates.md                      |  7 +++++++
 gcc/config/s390/s390.md                            | 24 ++++++++++++++--------
 gcc/testsuite/gcc.target/s390/loc-1.c              | 20 ++++++++++++++++++
 gcc/testsuite/gcc.target/s390/loc-2.c              | 20 ++++++++++++++++++
 .../gcc.target/s390/vector/vec-scalar-cmp-1.c      |  4 ++--
 5 files changed, 65 insertions(+), 10 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/s390/loc-1.c
 create mode 100644 gcc/testsuite/gcc.target/s390/loc-2.c

diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md
index e66f4a4..75e4cb8 100644
--- a/gcc/config/s390/predicates.md
+++ b/gcc/config/s390/predicates.md
@@ -182,6 +182,13 @@
   return s390_contiguous_bitmask_p (INTVAL (op), GET_MODE_BITSIZE (mode), NULL, NULL);
 })
 
+;; Return true if OP is ligitimate for any LOC instruction.
+
+(define_predicate "loc_operand"
+  (ior (match_operand 0 "nonimmediate_operand")
+      (and (match_code "const_int")
+	   (match_test "INTVAL (op) <= 32767 && INTVAL (op) >= -32768"))))
+
 ;; operators --------------------------------------------------------------
 
 ;; Return nonzero if OP is a valid comparison operator
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index f8c61a8..6d8d041 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -483,7 +483,7 @@
   (const (symbol_ref "s390_tune_attr")))
 
 (define_attr "cpu_facility"
-  "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec"
+  "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec,z13"
   (const_string "standard"))
 
 (define_attr "enabled" ""
@@ -528,7 +528,12 @@
 
          (and (eq_attr "cpu_facility" "vec")
               (match_test "TARGET_VX"))
-	 (const_int 1)]
+	 (const_int 1)
+
+         (and (eq_attr "cpu_facility" "z13")
+              (match_test "TARGET_Z13"))
+	 (const_int 1)
+	 ]
 	(const_int 0)))
 
 ;; Pipeline description for z900.  For lack of anything better,
@@ -6309,21 +6314,23 @@
 				     XEXP (operands[1], 1));
 })
 
-; locr, loc, stoc, locgr, locg, stocg
+; locr, loc, stoc, locgr, locg, stocg, lochi, locghi
 (define_insn_and_split "*mov<mode>cc"
-  [(set (match_operand:GPR 0 "nonimmediate_operand"   "=d,d,d,d,S,S,&d")
+  [(set (match_operand:GPR 0 "nonimmediate_operand"   "=d,d,d,d,d,d,S,S,&d")
 	(if_then_else:GPR
 	  (match_operator 1 "s390_comparison"
-	    [(match_operand 2 "cc_reg_operand"        " c,c,c,c,c,c,c")
+	    [(match_operand 2 "cc_reg_operand"        " c,c,c,c,c,c,c,c,c")
 	     (match_operand 5 "const_int_operand"     "")])
-	  (match_operand:GPR 3 "nonimmediate_operand" " d,0,S,0,d,0,S")
-	  (match_operand:GPR 4 "nonimmediate_operand" " 0,d,0,S,0,d,S")))]
+	  (match_operand:GPR 3 "loc_operand" " d,0,S,0,K,0,d,0,S")
+	  (match_operand:GPR 4 "loc_operand" " 0,d,0,S,0,K,0,d,S")))]
   "TARGET_Z196"
   "@
    loc<g>r%C1\t%0,%3
    loc<g>r%D1\t%0,%4
    loc<g>%C1\t%0,%3
    loc<g>%D1\t%0,%4
+   loc<g>hi%C1\t%0,%h3
+   loc<g>hi%D1\t%0,%h4
    stoc<g>%C1\t%3,%0
    stoc<g>%D1\t%4,%0
    #"
@@ -6340,7 +6347,8 @@
 	 (match_dup 0)
 	 (match_dup 4)))]
   ""
-  [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
+  [(set_attr "op_type" "RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY,*")
+   (set_attr "cpu_facility" "*,*,*,*,z13,z13,*,*,*")])
 
 ;;
 ;;- Multiply instructions.
diff --git a/gcc/testsuite/gcc.target/s390/loc-1.c b/gcc/testsuite/gcc.target/s390/loc-1.c
new file mode 100644
index 0000000..69f9c04
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/loc-1.c
@@ -0,0 +1,20 @@
+/* Test load on condition patterns.  */
+
+/* { dg-do compile { target { lp64 } } } */
+/* { dg-options "-O3 -march=z13 -mzarch -fno-asynchronous-unwind-tables" } */
+
+unsigned long locgr (unsigned long rc, unsigned long cond, unsigned long val)
+{
+  if (cond)
+    rc = val;
+  return rc;
+}
+/* { dg-final { scan-assembler "locgr:\n\tltgr\t%r3,%r3\n\tlocgrne\t%r2,%r4\n\tbr\t%r14\n" } } */
+
+long locghi (long rc, long cond)
+{
+  if (cond)
+    rc = (long)-1;
+  return rc;
+}
+/* { dg-final { scan-assembler "locghi:\n\tltgr\t%r3,%r3\n\tlocghine\t%r2,-1\n\tbr\t%r14\n" } } */
diff --git a/gcc/testsuite/gcc.target/s390/loc-2.c b/gcc/testsuite/gcc.target/s390/loc-2.c
new file mode 100644
index 0000000..ad4d23a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/loc-2.c
@@ -0,0 +1,20 @@
+/* Test load on condition patterns.  */
+
+/* { dg-do compile { target { ! lp64 } } } */
+/* { dg-options "-O3 -march=z13 -mzarch -fno-asynchronous-unwind-tables" } */
+
+unsigned long locr (unsigned int rc, unsigned long cond, unsigned long val)
+{
+  if (cond)
+    rc = (unsigned int)val;
+  return rc;
+}
+/* { dg-final { scan-assembler "locr:\n\tltr\t%r3,%r3\n\tlocrne\t%r2,%r4\n\tbr\t%r14\n" } } */
+
+long lochi (long rc, long cond)
+{
+  if (cond)
+    rc = (int)2;
+  return rc;
+}
+/* { dg-final { scan-assembler "lochi:\n\tltr\t%r3,%r3\n\tlochine\t%r2,2\n\tbr\t%r14\n" } } */
diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-scalar-cmp-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-scalar-cmp-1.c
index b79120f..5f63eda 100644
--- a/gcc/testsuite/gcc.target/s390/vector/vec-scalar-cmp-1.c
+++ b/gcc/testsuite/gcc.target/s390/vector/vec-scalar-cmp-1.c
@@ -8,8 +8,8 @@
 /* { dg-final { scan-assembler-times "wfchedbs\t%v\[0-9\]*,%v2,%v0" 1 } } */
 /* { dg-final { scan-assembler-times "wfchdbs\t%v\[0-9\]*,%v2,%v0" 1 } } */
 /* { dg-final { scan-assembler-times "wfchedbs\t%v\[0-9\]*,%v2,%v0" 1 } } */
-/* { dg-final { scan-assembler-times "locrne" 5 } } */
-/* { dg-final { scan-assembler-times "locrno" 1 } } */
+/* { dg-final { scan-assembler-times "lochine" 5 } } */
+/* { dg-final { scan-assembler-times "lochino" 1 } } */
 
 
 int
-- 
2.3.0

