From patchwork Thu May 19 11:18:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dominik Vogt X-Patchwork-Id: 623942 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3r9T8b5t9Xz9sD9 for ; Thu, 19 May 2016 21:18:39 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=LM3WgGoG; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:reply-to:references:mime-version :content-type:in-reply-to; q=dns; s=default; b=Zy+7k9YF3RNFFy6zr OMMqasqYcsrHikQTKHXTkysX2M9HpEH2u87hr9DISD7fuvLibBaAYgD+jE/RGQw7 kPOoQpUQQ3AtDTtSfAVGUwuxOpcCALFgxAW7dxsLV0N/OdaWflBdlo/OFD6WT7cF m1WxwGQHxjFpapeH8USqlfW01k= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:reply-to:references:mime-version :content-type:in-reply-to; s=default; bh=+SAEWuj4BEwCC6zPL3Bcw9o Iy8U=; b=LM3WgGoG//3bhtavdczRQYkrih7DXDU9UORbXv42w/lYbgR0bx8J1A8 CWp+5bPT3dUlVFz4H544ziCSgoLeYd8Cgnc7e+tOJ6yI5s7KxBxK89RIZyn5hOSz 32fILoUv0BebEsSS3WQPThJmVxv7NLwqW9K/CCoxWYrK49rKfVCA= Received: (qmail 117658 invoked by alias); 19 May 2016 11:18:30 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 117640 invoked by uid 89); 19 May 2016 11:18:29 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL, BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=costing, unforeseeable, ist X-HELO: e06smtp07.uk.ibm.com Received: from e06smtp07.uk.ibm.com (HELO e06smtp07.uk.ibm.com) (195.75.94.103) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (CAMELLIA256-SHA encrypted) ESMTPS; Thu, 19 May 2016 11:18:26 +0000 Received: from localhost by e06smtp07.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 19 May 2016 12:18:21 +0100 X-IBM-Helo: d06dlp03.portsmouth.uk.ibm.com X-IBM-MailFrom: vogt@linux.vnet.ibm.com X-IBM-RcptTo: gcc-patches@gcc.gnu.org Received: from b06cxnps4074.portsmouth.uk.ibm.com (d06relay11.portsmouth.uk.ibm.com [9.149.109.196]) by d06dlp03.portsmouth.uk.ibm.com (Postfix) with ESMTP id 87B671B08061 for ; Thu, 19 May 2016 12:19:17 +0100 (BST) Received: from d06av09.portsmouth.uk.ibm.com (d06av09.portsmouth.uk.ibm.com [9.149.37.250]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u4JBIKUZ24576320 for ; Thu, 19 May 2016 11:18:20 GMT Received: from d06av09.portsmouth.uk.ibm.com (localhost [127.0.0.1]) by d06av09.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id u4JBIKoL007460 for ; Thu, 19 May 2016 05:18:20 -0600 Received: from bl3ahm9f.de.ibm.com (dyn-9-152-212-21.boeblingen.de.ibm.com [9.152.212.21]) by d06av09.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id u4JBIKLS007447; Thu, 19 May 2016 05:18:20 -0600 Received: from dvogt by bl3ahm9f.de.ibm.com with local (Exim 4.76) (envelope-from ) id 1b3Ly7-0006Z8-FS; Thu, 19 May 2016 13:18:19 +0200 Date: Thu, 19 May 2016 12:18:19 +0100 From: Dominik Vogt To: Jeff Law Cc: Bernd Schmidt , gcc-patches@gcc.gnu.org, Andreas Krebbel , Ulrich Weigand Subject: Re: [PATCH v3] Take known zero bits into account when checking extraction. Message-ID: <20160519111819.GA24787@linux.vnet.ibm.com> Reply-To: vogt@linux.vnet.ibm.com Mail-Followup-To: vogt@linux.vnet.ibm.com, Jeff Law , Bernd Schmidt , gcc-patches@gcc.gnu.org, Andreas Krebbel , Ulrich Weigand References: <20160427082004.GE5082@linux.vnet.ibm.com> <20160510130655.GA4308@linux.vnet.ibm.com> <5731F8A2.6090202@redhat.com> <20160511074258.GA2730@linux.vnet.ibm.com> <5732EFEB.6050700@redhat.com> <20160511085235.GA8002@linux.vnet.ibm.com> <7825b1d8-18c4-b561-f6c7-5b6d45f6f402@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <7825b1d8-18c4-b561-f6c7-5b6d45f6f402@redhat.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16051911-0029-0000-0000-00001EC5171B X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused On Mon, May 16, 2016 at 01:09:36PM -0600, Jeff Law wrote: > On 05/11/2016 02:52 AM, Dominik Vogt wrote: > >On Wed, May 11, 2016 at 10:40:11AM +0200, Bernd Schmidt wrote: > >That's what I mentioned somewhere during the discussion. The s390 > >backend just uses COSTS_N_INSNS(1) for AND as well as ZERO_EXTEND, > >so this won't ever trigger. I just left the rtx_cost call in the > >patch for further discussion as Jeff said he liked the approach. > >We don't need it to achieve the behaviour we want for s390. > I liked it, just based on the general theory that we should be > comparing costs of a transform to the original much more often than > we currently do. > > If Bernd prefers it gone and you don't need it to achieve your > goals, then I won't object to the costing stuff going away. All right, third version attached, without the rtx_vost call; bootstrapped and regression tested on s390, s390x, x86_64. On Wed, Apr 27, 2016 at 09:20:05AM +0100, Dominik Vogt wrote: > The attached patch is a result of discussing an S/390 issue with > "and with complement" in some cases. > > https://gcc.gnu.org/ml/gcc/2016-03/msg00163.html > https://gcc.gnu.org/ml/gcc-patches/2016-04/msg01586.html > > Combine would merge a ZERO_EXTEND and a SET taking the known zero > bits into account, resulting in an AND. Later on, > make_compound_operation() fails to replace that with a ZERO_EXTEND > which we get for free on S/390 but leaves the AND, eventually > resulting in two consecutive AND instructions. > > The current code in make_compound_operation() that detects > opportunities for ZERO_EXTEND does not work here because it does > not take the known zero bits into account: > > /* If the constant is one less than a power of two, this might be > representable by an extraction even if no shift is present. > If it doesn't end up being a ZERO_EXTEND, we will ignore it unless > we are in a COMPARE. */ > else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0) > new_rtx = make_extraction (mode, > make_compound_operation (XEXP (x, 0), > next_code), > 0, NULL_RTX, i, 1, 0, in_code == COMPARE); > > An attempt to use the zero bits in the above conditions resulted > in many situations that generated worse code, so the patch tries > to fix this in a more conservative way. While the effect is > completely positive on S/390, this will very likely have > unforeseeable consequences on other targets. > > Bootstrapped and regression tested on s390 and s390x only at the > moment. Ciao Dominik ^_^ ^_^ From dde191ad76255c0826a546b03f441af748edbd77 Mon Sep 17 00:00:00 2001 From: Dominik Vogt Date: Tue, 12 Apr 2016 09:53:46 +0100 Subject: [PATCH] Take known zero bits into account when checking extraction. Allows AND Insns with a const_int operand to be expressed as ZERO_EXTEND if the operand ist a power of 2 - 1 even with the known zero bits masked out. --- gcc/combine.c | 28 ++++++++++++++++++ gcc/testsuite/gcc.dg/zero_bits_compound-1.c | 44 +++++++++++++++++++++++++++++ gcc/testsuite/gcc.dg/zero_bits_compound-2.c | 39 +++++++++++++++++++++++++ 3 files changed, 111 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/zero_bits_compound-1.c create mode 100644 gcc/testsuite/gcc.dg/zero_bits_compound-2.c diff --git a/gcc/combine.c b/gcc/combine.c index 3554f51..97d59d7 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -7988,6 +7988,34 @@ make_compound_operation (rtx x, enum rtx_code in_code) next_code), i, NULL_RTX, 1, 1, 0, 1); + /* If the one operand is a paradoxical subreg of a register or memory and + the constant (limited to the smaller mode) has only zero bits where + the sub expression has known zero bits, this can be expressed as + a zero_extend. */ + else if (GET_CODE (XEXP (x, 0)) == SUBREG) + { + rtx sub; + + sub = XEXP (XEXP (x, 0), 0); + machine_mode sub_mode = GET_MODE (sub); + if ((REG_P (sub) || MEM_P (sub)) + && GET_MODE_PRECISION (sub_mode) < mode_width) + { + unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (sub_mode); + unsigned HOST_WIDE_INT mask; + + /* original AND constant with all the known zero bits set */ + mask = UINTVAL (XEXP (x, 1)) | (~nonzero_bits (sub, sub_mode)); + if ((mask & mode_mask) == mode_mask) + { + new_rtx = make_compound_operation (sub, next_code); + new_rtx = make_extraction (mode, new_rtx, 0, 0, + GET_MODE_PRECISION (sub_mode), + 1, 0, in_code == COMPARE); + } + } + } + break; case LSHIFTRT: diff --git a/gcc/testsuite/gcc.dg/zero_bits_compound-1.c b/gcc/testsuite/gcc.dg/zero_bits_compound-1.c new file mode 100644 index 0000000..731907f --- /dev/null +++ b/gcc/testsuite/gcc.dg/zero_bits_compound-1.c @@ -0,0 +1,44 @@ +/* Test whether an AND mask or'ed with the know zero bits that equals a mode + mask is a candidate for zero extendion. */ + +/* Note: This test requires that char, int and long have different sizes and the + target has a way to do 32 -> 64 bit zero extension other than AND. Targets + that fail the test because they do not satisfy these preconditions can skip + it. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O3 -dP" } */ + +unsigned long foo (unsigned char c) +{ + unsigned long l; + unsigned int i; + + i = ((unsigned int)c) << 8; + i |= ((unsigned int)c) << 20; + asm volatile ("":::); + i = i & 0x0ff0ff00; + asm volatile ("":::); + l = (unsigned long)i; + + return l; +} + +unsigned long bar (unsigned char c) +{ + unsigned long l; + unsigned int i; + + i = ((unsigned int)c) << 8; + i |= ((unsigned int)c) << 20; + asm volatile ("":::); + i = i & 0x0ffffff0; + asm volatile ("":::); + l = (unsigned long)i; + + return l; +} + +/* Check that no pattern containing an AND expression was used. */ +/* { dg-final { scan-assembler-not "\\(and:" } } */ diff --git a/gcc/testsuite/gcc.dg/zero_bits_compound-2.c b/gcc/testsuite/gcc.dg/zero_bits_compound-2.c new file mode 100644 index 0000000..a509966 --- /dev/null +++ b/gcc/testsuite/gcc.dg/zero_bits_compound-2.c @@ -0,0 +1,39 @@ +/* Test whether an AND mask or'ed with the know zero bits that equals a mode + mask is a candidate for zero extendion. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O3 -dP" } */ + +unsigned long foo (unsigned char c) +{ + unsigned long l; + unsigned int i; + + i = ((unsigned int)c) << 8; + i |= ((unsigned int)c) << 20; + asm volatile ("":::); + i = i & 0x0fe0fe00; + asm volatile ("":::); + l = (unsigned long)i; + + return l; +} + +unsigned long bar (unsigned char c) +{ + unsigned long l; + unsigned int i; + + i = ((unsigned int)c) << 8; + i |= ((unsigned int)c) << 20; + asm volatile ("":::); + i = i & 0x07f007f0; + asm volatile ("":::); + l = (unsigned long)i; + + return l; +} + +/* Check that an AND expression was used. */ +/* { dg-final { scan-assembler-times "\\(and:" 2 } } */ -- 2.3.0