From patchwork Fri Apr 29 15:42:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Enkovich X-Patchwork-Id: 616872 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qxHzh3HMXz9t3k for ; Sat, 30 Apr 2016 01:43:41 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=IufF1Tfu; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; q=dns; s=default; b=CKw0b7gmRZ5Ss/a9KJZt+9STRosxWdA7gaNlrny00dam9jkJaQ UOC9MJT5gdVDZvvKw4W1g9XradeNUYWaKi0qZpeE4sHp6fVJHZevmG+m2E1ksjBb o7vWaeTJV6rUe8LwvCyPntDj6Imn3bwBXAnjJdYdZDgw3PoS+JYT31qsk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; s= default; bh=2pHXCCCLXg6TdKoK5HvkzpYvW/4=; b=IufF1Tfuh2lip7yvOLzS Gkn0zOvcljxjyNlmeaNhZmPQmUH8WWdsz9YMbjxDn94muwTH+av4A1tfiyx42Kc7 NjdOzRraJZZhnxfbA36oJpiTzymkAjTXltuEdWhIbGu2U71/0y2hDW6ZYRYUFXjT 5r07SfhXy2EKcYLWtAgRSfE= Received: (qmail 113291 invoked by alias); 29 Apr 2016 15:43:34 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 113280 invoked by uid 89); 29 Apr 2016 15:43:33 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=!reg_p, !REG_P, ilya.enkovich@intel.com, ilyaenkovichintelcom X-HELO: mail-wm0-f68.google.com Received: from mail-wm0-f68.google.com (HELO mail-wm0-f68.google.com) (74.125.82.68) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Fri, 29 Apr 2016 15:43:17 +0000 Received: by mail-wm0-f68.google.com with SMTP id n129so5905466wmn.1 for ; Fri, 29 Apr 2016 08:43:17 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:mime-version :content-disposition:user-agent; bh=eWPi8KS89uEy+uqJwZLOnvcZzhcjOrbsz967yJtPWgM=; b=R0BuKQEo7V+ilAo402XTGU3qqwywmTe72Q5Jh0u+gkfrvL8oqkIXzu0bmPA0P3kk8L tB6JGWHQ9B/850/jzinGp0427Lq16DuOlS3qbeQMzW4U+gidq1s69XIEhn6xNclN/iY8 vGpwdhmpFhbgUias77DB154AsDDHyJstNCEOV86e7wvAODLguiKYo+cFF56zLQN2mIf8 JKQXmeFF7zUFkFTrhexDwv86br0J071gDpPFl1AipJN0cZyPMJD3Y8XKb9OI03zzzA4z n6CcAhwmoN0rb6vGfu0T+3CrB8b2nWewrvY+LPSRBg55CNiqW22pDC6wx4mnzDncqGea BN7A== X-Gm-Message-State: AOPr4FU2lzSWYd9VxwIYg894BIk5MICelU9uk+YIAQHz9641hw1D6WCAzKEwrGWaRdY6pA== X-Received: by 10.194.58.138 with SMTP id r10mr22371702wjq.153.1461944594897; Fri, 29 Apr 2016 08:43:14 -0700 (PDT) Received: from msticlxl57.ims.intel.com (irdmzpr02-ext.ir.intel.com. [192.198.151.37]) by smtp.gmail.com with ESMTPSA id 186sm3883676wmk.2.2016.04.29.08.43.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 29 Apr 2016 08:43:14 -0700 (PDT) Date: Fri, 29 Apr 2016 18:42:19 +0300 From: Ilya Enkovich To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, hjl.tools@gmail.com Subject: [PATCH, i386, PR target/70799, 1/2] Support constants in STV pass (DImode) Message-ID: <20160429154219.GC6099@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.23 (2014-03-12) X-IsSubscribed: yes Hi, As the first part of PR70799 fix I'd like to add constants support for DI-STV pass (which is also related to PR70763). This patch adds CONST_INT support as insn operands and extends cost model accordingly. Bootstrapped and regtested on x86_64-unknown-linux-gnu{-m32}. OK for trunk? Thanks, Ilya --- gcc/ 2016-04-29 Ilya Enkovich PR target/70799 PR target/70763 * config/i386/i386.c (dimode_scalar_to_vector_candidate_p): Allow integer constants. (dimode_scalar_chain::vector_const_cost): New. (dimode_scalar_chain::compute_convert_gain): Handle constants. (dimode_scalar_chain::convert_op): Likewise. (dimode_scalar_chain::convert_insn): Likewise. gcc/testsuite/ 2016-04-29 Ilya Enkovich * gcc.target/i386/pr70799-1.c: New test. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 9680aaf..ff6b4bc 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -2789,7 +2789,8 @@ dimode_scalar_to_vector_candidate_p (rtx_insn *insn) return convertible_comparison_p (insn); /* We are interested in DImode promotion only. */ - if (GET_MODE (src) != DImode + if ((GET_MODE (src) != DImode + && !CONST_INT_P (src)) || GET_MODE (dst) != DImode) return false; @@ -2809,24 +2810,31 @@ dimode_scalar_to_vector_candidate_p (rtx_insn *insn) return true; case MEM: + case CONST_INT: return REG_P (dst); default: return false; } - if (!REG_P (XEXP (src, 0)) && !MEM_P (XEXP (src, 0)) + if (!REG_P (XEXP (src, 0)) + && !MEM_P (XEXP (src, 0)) + && !CONST_INT_P (XEXP (src, 0)) /* Check for andnot case. */ && (GET_CODE (src) != AND || GET_CODE (XEXP (src, 0)) != NOT || !REG_P (XEXP (XEXP (src, 0), 0)))) return false; - if (!REG_P (XEXP (src, 1)) && !MEM_P (XEXP (src, 1))) + if (!REG_P (XEXP (src, 1)) + && !MEM_P (XEXP (src, 1)) + && !CONST_INT_P (XEXP (src, 1))) return false; - if (GET_MODE (XEXP (src, 0)) != DImode - || GET_MODE (XEXP (src, 1)) != DImode) + if ((GET_MODE (XEXP (src, 0)) != DImode + && !CONST_INT_P (XEXP (src, 0))) + || (GET_MODE (XEXP (src, 1)) != DImode + && !CONST_INT_P (XEXP (src, 1)))) return false; return true; @@ -3120,6 +3128,7 @@ class dimode_scalar_chain : public scalar_chain void convert_reg (unsigned regno); void make_vector_copies (unsigned regno); void convert_registers (); + int vector_const_cost (rtx exp); }; class timode_scalar_chain : public scalar_chain @@ -3328,6 +3337,19 @@ scalar_chain::build (bitmap candidates, unsigned insn_uid) BITMAP_FREE (queue); } +/* Return a cost of building a vector costant + instead of using a scalar one. */ + +int +dimode_scalar_chain::vector_const_cost (rtx exp) +{ + gcc_assert (CONST_INT_P (exp)); + + if (standard_sse_constant_p (exp, V2DImode)) + return COSTS_N_INSNS (1); + return ix86_cost->sse_load[1]; +} + /* Compute a gain for chain conversion. */ int @@ -3359,11 +3381,25 @@ dimode_scalar_chain::compute_convert_gain () || GET_CODE (src) == IOR || GET_CODE (src) == XOR || GET_CODE (src) == AND) - gain += ix86_cost->add; + { + gain += ix86_cost->add; + if (CONST_INT_P (XEXP (src, 0))) + gain -= vector_const_cost (XEXP (src, 0)); + if (CONST_INT_P (XEXP (src, 1))) + gain -= vector_const_cost (XEXP (src, 1)); + } else if (GET_CODE (src) == COMPARE) { /* Assume comparison cost is the same. */ } + else if (GET_CODE (src) == CONST_INT) + { + if (REG_P (dst)) + gain += COSTS_N_INSNS (2); + else if (MEM_P (dst)) + gain += 2 * ix86_cost->int_store[2] - ix86_cost->sse_store[1]; + gain -= vector_const_cost (src); + } else gcc_unreachable (); } @@ -3639,6 +3675,22 @@ dimode_scalar_chain::convert_op (rtx *op, rtx_insn *insn) } *op = gen_rtx_SUBREG (V2DImode, *op, 0); } + else if (CONST_INT_P (*op)) + { + rtx cst = const0_rtx; + rtx tmp = gen_rtx_SUBREG (V2DImode, gen_reg_rtx (DImode), 0); + + /* Prefer all ones vector in case of -1. */ + if (constm1_operand (*op, GET_MODE (*op))) + cst = *op; + cst = gen_rtx_CONST_VECTOR (V2DImode, gen_rtvec (2, *op, cst)); + + if (!standard_sse_constant_p (cst, V2DImode)) + cst = validize_mem (force_const_mem (V2DImode, cst)); + + emit_insn_before (gen_move_insn (tmp, cst), insn); + *op = tmp; + } else { gcc_assert (SUBREG_P (*op)); @@ -3711,6 +3763,10 @@ dimode_scalar_chain::convert_insn (rtx_insn *insn) UNSPEC_PTEST); break; + case CONST_INT: + convert_op (&src, insn); + break; + default: gcc_unreachable (); } diff --git a/gcc/testsuite/gcc.target/i386/pr70799-1.c b/gcc/testsuite/gcc.target/i386/pr70799-1.c new file mode 100644 index 0000000..0abbfb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr70799-1.c @@ -0,0 +1,41 @@ +/* PR target/pr70799 */ +/* { dg-do compile { target { ia32 } } } */ +/* { dg-options "-O2 -march=slm" } */ +/* { dg-final { scan-assembler "pxor" } } */ +/* { dg-final { scan-assembler "pcmpeqd" } } */ +/* { dg-final { scan-assembler "movdqa\[ \\t\]+.LC0" } } */ + +long long a, b, c; + +void test1 (void) +{ + long long t; + if (a) + t = 0LL; + else + t = b; + a = c & t; + b = c | t; +} + +void test2 (void) +{ + long long t; + if (a) + t = -1LL; + else + t = b; + a = c & t; + b = c | t; +} + +void test3 (void) +{ + long long t; + if (a) + t = 0xf0f0f0f0f0f0f0f0LL; + else + t = b; + a = c & t; + b = c | t; +}