diff mbox

PR target/67995: __attribute__ ((target("arch=XXX"))) enables unsupported ISA

Message ID 20151016223803.GA25108@intel.com
State New
Headers show

Commit Message

H.J. Lu Oct. 16, 2015, 10:38 p.m. UTC 
When processing __attribute__ ((target("arch=XXX"))), we should clear
the ISA bits in x_ix86_isa_flags first to avoid leaking ISA from
command line.

Tested on x86-64.  OK for trunk?

Thanks.

H.J.
---
gcc/

	PR target/67995
	* config/i386/i386.c (ix86_valid_target_attribute_tree): If
	arch= is set,  clear all bits in x_ix86_isa_flags, except for
	ISA_64BIT, ABI_64, ABI_X32, and CODE16.

gcc/testsuite/

	PR target/67995
	* gcc.target/i386/pr67995-1.c: New test.
	* gcc.target/i386/pr67995-2.c: Likewise.
	* gcc.target/i386/pr67995-3.c: Likewise.
---
 gcc/config/i386/i386.c                    | 13 ++++++++++++-
 gcc/testsuite/gcc.target/i386/pr67995-1.c | 16 ++++++++++++++++
 gcc/testsuite/gcc.target/i386/pr67995-2.c | 16 ++++++++++++++++
 gcc/testsuite/gcc.target/i386/pr67995-3.c | 16 ++++++++++++++++
 4 files changed, 60 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr67995-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/pr67995-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/pr67995-3.c

Comments

Uros Bizjak Oct. 19, 2015, 11:08 a.m. UTC | #1 
On Sat, Oct 17, 2015 at 12:38 AM, H.J. Lu <hongjiu.lu@intel.com> wrote:
> When processing __attribute__ ((target("arch=XXX"))), we should clear
> the ISA bits in x_ix86_isa_flags first to avoid leaking ISA from
> command line.
>
> Tested on x86-64.  OK for trunk?

OK.

Thanks,
Uros.

> Thanks.
>
> H.J.
> ---
> gcc/
>
>         PR target/67995
>         * config/i386/i386.c (ix86_valid_target_attribute_tree): If
>         arch= is set,  clear all bits in x_ix86_isa_flags, except for
>         ISA_64BIT, ABI_64, ABI_X32, and CODE16.
>
> gcc/testsuite/
>
>         PR target/67995
>         * gcc.target/i386/pr67995-1.c: New test.
>         * gcc.target/i386/pr67995-2.c: Likewise.
>         * gcc.target/i386/pr67995-3.c: Likewise.
> ---
>  gcc/config/i386/i386.c                    | 13 ++++++++++++-
>  gcc/testsuite/gcc.target/i386/pr67995-1.c | 16 ++++++++++++++++
>  gcc/testsuite/gcc.target/i386/pr67995-2.c | 16 ++++++++++++++++
>  gcc/testsuite/gcc.target/i386/pr67995-3.c | 16 ++++++++++++++++
>  4 files changed, 60 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.target/i386/pr67995-1.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/pr67995-2.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/pr67995-3.c
>
> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> index d0e1f4c..b0281c9 100644
> --- a/gcc/config/i386/i386.c
> +++ b/gcc/config/i386/i386.c
> @@ -6145,7 +6145,18 @@ ix86_valid_target_attribute_tree (tree args,
>        /* If we are using the default tune= or arch=, undo the string assigned,
>          and use the default.  */
>        if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
> -       opts->x_ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
> +       {
> +         opts->x_ix86_arch_string
> +           = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
> +
> +         /* If arch= is set,  clear all bits in x_ix86_isa_flags,
> +            except for ISA_64BIT, ABI_64, ABI_X32, and CODE16.  */
> +         opts->x_ix86_isa_flags &= (OPTION_MASK_ISA_64BIT
> +                                    | OPTION_MASK_ABI_64
> +                                    | OPTION_MASK_ABI_X32
> +                                    | OPTION_MASK_CODE16);
> +
> +       }
>        else if (!orig_arch_specified)
>         opts->x_ix86_arch_string = NULL;
>
> diff --git a/gcc/testsuite/gcc.target/i386/pr67995-1.c b/gcc/testsuite/gcc.target/i386/pr67995-1.c
> new file mode 100644
> index 0000000..072b1fe
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr67995-1.c
> @@ -0,0 +1,16 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=haswell" } */
> +
> +unsigned int
> +__attribute__ ((target("arch=core2")))
> +__x86_rdrand(void)
> +{
> +  unsigned int retries = 100;
> +  unsigned int val;
> +
> +  while (__builtin_ia32_rdrand32_step(&val) == 0) /* { dg-error "needs isa option" } */
> +    if (--retries == 0)
> +      return 0;
> +
> +  return val;
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/pr67995-2.c b/gcc/testsuite/gcc.target/i386/pr67995-2.c
> new file mode 100644
> index 0000000..632bb63
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr67995-2.c
> @@ -0,0 +1,16 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=core2" } */
> +
> +unsigned int
> +__attribute__ ((target("arch=haswell")))
> +__x86_rdrand(void)
> +{
> +  unsigned int retries = 100;
> +  unsigned int val;
> +
> +  while (__builtin_ia32_rdrand32_step(&val) == 0)
> +    if (--retries == 0)
> +      return 0;
> +
> +  return val;
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/pr67995-3.c b/gcc/testsuite/gcc.target/i386/pr67995-3.c
> new file mode 100644
> index 0000000..11993b7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr67995-3.c
> @@ -0,0 +1,16 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=core2" } */
> +
> +unsigned int
> +__attribute__ ((target("rdrnd")))
> +__x86_rdrand(void)
> +{
> +  unsigned int retries = 100;
> +  unsigned int val;
> +
> +  while (__builtin_ia32_rdrand32_step(&val) == 0)
> +    if (--retries == 0)
> +      return 0;
> +
> +  return val;
> +}
> --
> 2.4.3
>
diff mbox

Patch

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index d0e1f4c..b0281c9 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -6145,7 +6145,18 @@  ix86_valid_target_attribute_tree (tree args,
       /* If we are using the default tune= or arch=, undo the string assigned,
 	 and use the default.  */
       if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
-	opts->x_ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
+	{
+	  opts->x_ix86_arch_string
+	    = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
+
+	  /* If arch= is set,  clear all bits in x_ix86_isa_flags,
+	     except for ISA_64BIT, ABI_64, ABI_X32, and CODE16.  */
+	  opts->x_ix86_isa_flags &= (OPTION_MASK_ISA_64BIT
+				     | OPTION_MASK_ABI_64
+				     | OPTION_MASK_ABI_X32
+				     | OPTION_MASK_CODE16);
+
+	}
       else if (!orig_arch_specified)
 	opts->x_ix86_arch_string = NULL;
 
diff --git a/gcc/testsuite/gcc.target/i386/pr67995-1.c b/gcc/testsuite/gcc.target/i386/pr67995-1.c
new file mode 100644
index 0000000..072b1fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr67995-1.c
@@ -0,0 +1,16 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=haswell" } */
+
+unsigned int
+__attribute__ ((target("arch=core2")))
+__x86_rdrand(void)
+{
+  unsigned int retries = 100;
+  unsigned int val;
+
+  while (__builtin_ia32_rdrand32_step(&val) == 0) /* { dg-error "needs isa option" } */
+    if (--retries == 0)
+      return 0;
+
+  return val;
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr67995-2.c b/gcc/testsuite/gcc.target/i386/pr67995-2.c
new file mode 100644
index 0000000..632bb63
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr67995-2.c
@@ -0,0 +1,16 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=core2" } */
+
+unsigned int
+__attribute__ ((target("arch=haswell")))
+__x86_rdrand(void)
+{
+  unsigned int retries = 100;
+  unsigned int val;
+
+  while (__builtin_ia32_rdrand32_step(&val) == 0)
+    if (--retries == 0)
+      return 0;
+
+  return val;
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr67995-3.c b/gcc/testsuite/gcc.target/i386/pr67995-3.c
new file mode 100644
index 0000000..11993b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr67995-3.c
@@ -0,0 +1,16 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=core2" } */
+
+unsigned int
+__attribute__ ((target("rdrnd")))
+__x86_rdrand(void)
+{
+  unsigned int retries = 100;
+  unsigned int val;
+
+  while (__builtin_ia32_rdrand32_step(&val) == 0)
+    if (--retries == 0)
+      return 0;
+
+  return val;
+}