From patchwork Wed Jun 24 00:53:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Modra X-Patchwork-Id: 487893 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id BF68C14031E for ; Wed, 24 Jun 2015 10:53:22 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=pQya/+FC; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; q=dns; s=default; b=wO+/ECwCzpiEhqNv8 jqBmTn2lOcCmwS+NxS7IlrF9jzNHOgM2MTaqElkgdRD8qdiXhiRFF4ZaJPsp+od0 hJJrtbSu+EMo7BQQpAqt44Jxjg3orjoNasStUGnIOH6fvEuvftHcBXUQLmT11pEj 3dqKOJawTvoWWdOqrd5I43RENQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; s=default; bh=y/GqIgyijElUbLU0EopsI1W IOm4=; b=pQya/+FC63/at5BOS+buABBa90Lxi9E15SbGVSBN4G00bqGwvixDS4h g5Na5wBqlCvKGYJXTk9h5f9la/x6AfJwyilxYakVSoIVd2cCkxZ6RzbRuaP1N/Ll TP71G/2QbtItpuK2h0c0c7d8lF72NzF0x1DJiaKW+wWXazrdqKxQ= Received: (qmail 48323 invoked by alias); 24 Jun 2015 00:53:12 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 47625 invoked by uid 89); 24 Jun 2015 00:53:12 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-pa0-f48.google.com Received: from mail-pa0-f48.google.com (HELO mail-pa0-f48.google.com) (209.85.220.48) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Wed, 24 Jun 2015 00:53:11 +0000 Received: by paceq1 with SMTP id eq1so17378301pac.3 for ; Tue, 23 Jun 2015 17:53:09 -0700 (PDT) X-Received: by 10.66.139.138 with SMTP id qy10mr75747931pab.30.1435107189320; Tue, 23 Jun 2015 17:53:09 -0700 (PDT) Received: from bubble.grove.modra.org (CPE-58-160-155-134.oycza5.sa.bigpond.net.au. [58.160.155.134]) by mx.google.com with ESMTPSA id cd10sm24650551pac.7.2015.06.23.17.53.08 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Jun 2015 17:53:08 -0700 (PDT) Received: by bubble.grove.modra.org (Postfix, from userid 1000) id 9776FEA0074; Wed, 24 Jun 2015 10:23:04 +0930 (ACST) Date: Wed, 24 Jun 2015 10:23:04 +0930 From: Alan Modra To: gcc-patches@gcc.gnu.org Cc: David Edelsohn Subject: [RS6000 4/7] rldic in rotate and mask patterns Message-ID: <20150624005304.GY1723@bubble.grove.modra.org> Mail-Followup-To: gcc-patches@gcc.gnu.org, David Edelsohn References: <20150624004649.GU1723@bubble.grove.modra.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20150624004649.GU1723@bubble.grove.modra.org> User-Agent: Mutt/1.5.23 (2014-03-12) X-IsSubscribed: yes rldic can support ROTATE as well as ASHIFT inside an AND, provided the AND mask has exactly the shift count low zeros. The added rotate patterns are needed to support the next patch that removes the mask64_2_operand patterns, and may be generally useful too. Note that the costing for the ROTATEs was handled by the last patch. * config/rs6000/rs6000.md (rotshift): New code iterator. (rldic__1, rldic__2, rldic__3, +splits): Rename from ashldi3_internal4..6. Use rotshift to support both rotate and ashift. diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index f28d48e..dafb04f 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -463,6 +463,8 @@ ; Logical operators. (define_code_iterator iorxor [ior xor]) +(define_code_iterator rotshift [rotate ashift]) + ; Signed/unsigned variants of ops. (define_code_iterator any_extend [sign_extend zero_extend]) (define_code_attr u [(sign_extend "") (zero_extend "u")]) @@ -5856,20 +5858,20 @@ "") -(define_insn "*ashldi3_internal4" +(define_insn "*rldic__1" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") - (match_operand:SI 2 "const_int_operand" "i")) + (and:DI (rotshift:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")) (match_operand:DI 3 "const_int_operand" "n")))] "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" "rldic %0,%1,%H2,%W3" [(set_attr "type" "shift")]) -(define_insn "*ashldi3_internal5" +(define_insn "*rldic__2" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC - (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "const_int_operand" "i,i")) + (and:DI (rotshift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "const_int_operand" "i,i")) (match_operand:DI 3 "const_int_operand" "n,n")) (const_int 0))) (clobber (match_scratch:DI 4 "=r,r"))] @@ -5884,30 +5886,30 @@ (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC - (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "const_int_operand" "")) + (and:DI (rotshift:DI (match_operand:DI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "const_int_operand" "")) (match_operand:DI 3 "const_int_operand" "")) (const_int 0))) (clobber (match_scratch:DI 4 ""))] "TARGET_POWERPC64 && reload_completed && includes_rldic_lshift_p (operands[2], operands[3])" [(set (match_dup 4) - (and:DI (ashift:DI (match_dup 1) (match_dup 2)) + (and:DI (rotshift:DI (match_dup 1) (match_dup 2)) (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") -(define_insn "*ashldi3_internal6" +(define_insn "*rldic__3" [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC - (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "const_int_operand" "i,i")) + (and:DI (rotshift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "const_int_operand" "i,i")) (match_operand:DI 3 "const_int_operand" "n,n")) (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] + (and:DI (rotshift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" "@ rldic. %0,%1,%H2,%W3 @@ -5919,22 +5921,23 @@ (define_split [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") (compare:CC - (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "const_int_operand" "")) + (and:DI (rotshift:DI (match_operand:DI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "const_int_operand" "")) (match_operand:DI 3 "const_int_operand" "")) (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "") - (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] + (and:DI (rotshift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWERPC64 && reload_completed && includes_rldic_lshift_p (operands[2], operands[3])" [(set (match_dup 0) - (and:DI (ashift:DI (match_dup 1) (match_dup 2)) + (and:DI (rotshift:DI (match_dup 1) (match_dup 2)) (match_dup 3))) (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") + (define_insn "*ashldi3_internal7" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")