@@ -1515,7 +1515,7 @@
addis %0,%1,%v2"
[(set_attr "type" "add")])
-(define_insn "addsi3_high"
+(define_insn "*addsi3_high"
[(set (match_operand:SI 0 "gpc_reg_operand" "=b")
(plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(high:SI (match_operand 2 "" ""))))]
@@ -2173,7 +2173,7 @@
operands[1] = force_reg (HImode, operands[1]);
})
-(define_insn "bswaphi2_internal"
+(define_insn "*bswaphi2_internal"
[(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
(bswap:HI
(match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
@@ -5873,7 +5873,7 @@
"rldic %0,%1,%H2,%W3"
[(set_attr "type" "shift")])
-(define_insn "ashldi3_internal5"
+(define_insn "*ashldi3_internal5"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(compare:CC
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
@@ -5952,7 +5952,7 @@
"rldicr %0,%1,%H2,%S3"
[(set_attr "type" "shift")])
-(define_insn "ashldi3_internal8"
+(define_insn "*ashldi3_internal8"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
(compare:CC
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")