From patchwork Fri Jun 5 23:44:16 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kaz Kojima X-Patchwork-Id: 481599 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 1C031140281 for ; Sat, 6 Jun 2015 09:44:32 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=seP7MOaC; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:to:subject:from:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=DYX4RV6IQEWGCYU9 CH4fkiHJMf560iPd3y4SqcrtnD5cni6PORXnMZ+3T7RniSTSwbWkdHqR6ZRKDmRg /FimzsVnab/m3N7qpfBmnUbfccABTPpwtx6rGiNuSc9toD86aQsO5PzXp+boBApZ VzBT80t+/54XQOAkmh3HxMa9rAs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :message-id:to:subject:from:mime-version:content-type :content-transfer-encoding; s=default; bh=6iBBRkb8dPiRCr6dp8PZb2 ktthU=; b=seP7MOaC0tVKJIh0Vo5DEwpyJuOvHdaJ+MIi6L6t2dCGxWMLoG/bhC BYmcXJR8u5uLSLZ3t7Drs7rkGZiTfkM5X/i1YfB6AhFq5JT38tdhdoXHR2CIwI+D p9QHSxVoFsSKQ8fb23ebDgyntJxRHLYSE3oK7/1cKhY5CDSL8Vgxg= Received: (qmail 15024 invoked by alias); 5 Jun 2015 23:44:24 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 14999 invoked by uid 89); 5 Jun 2015 23:44:23 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.6 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE, SPF_PASS, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: mo-sw.iij4u.or.jp Received: from mo-sw1501.iij4u.or.jp (HELO mo-sw.iij4u.or.jp) (210.130.239.241) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Fri, 05 Jun 2015 23:44:22 +0000 Received: by mo-sw.iij4u.or.jp (4u-mo-sw1501) id t55NiJci002977; Sat, 6 Jun 2015 08:44:19 +0900 Received: from localhost (24.26.30.125.dy.iij4u.or.jp [125.30.26.24]) by mbox.iij4u.or.jp (4u-mbox1501) id t55NiHnn032112; Sat, 6 Jun 2015 08:44:18 +0900 Date: Sat, 06 Jun 2015 08:44:16 +0900 (JST) Message-Id: <20150606.084416.409700869.kkojima@rr.iij4u.or.jp> To: gcc-patches@gcc.gnu.org Subject: [patch committed SH] Fix PR target/66410 From: Kaz Kojima Mime-Version: 1.0 X-IsSubscribed: yes The attached patch is to fix PR target/66410 which is an ICE in lra-assigns.c:assign_by_spills with -mlra. The insn *mov[qh]i has Snd/r alternative which is problematic when Snd is memory with index addressing and r is reloading with r0 because only r0 can become the index register on this target. The patch disparages this case for RA. It fixes PR and various libstdc++ test failures happen on trunk with -mlra. Tested on sh4-unknown-linux-gnu with no new failures. Committed. Regards, kaz --- 2015-06-05 Kaz Kojima PR target/66410 * config/sh/constraints.md (Sid, Ssd): New memory constraints. * config/sh/sh.md (*mov): Use Sid and Ssd alternatives instead of Snd. Disparage Sid/z alternative with '^'. diff --git a/config/sh/constraints.md b/config/sh/constraints.md index bd059a4..4d1eb2d 100644 --- a/config/sh/constraints.md +++ b/config/sh/constraints.md @@ -309,6 +309,19 @@ (and (match_code "mem") (match_test "! satisfies_constraint_Sdd (op)"))) +(define_memory_constraint "Sid" + "A memory reference that uses index addressing." + (and (match_code "mem") + (match_code "plus" "0") + (match_code "reg" "00") + (match_code "reg" "01"))) + +(define_memory_constraint "Ssd" + "A memory reference that excludes index and displacement addressing." + (and (match_code "mem") + (match_test "! satisfies_constraint_Sid (op)") + (match_test "! satisfies_constraint_Sdd (op)"))) + (define_memory_constraint "Sbv" "A memory reference, as used in SH2A bclr.b, bset.b, etc." (and (match_test "MEM_P (op) && GET_MODE (op) == QImode") diff --git a/config/sh/sh.md b/config/sh/sh.md index 634a612..2d10ddb 100644 --- a/config/sh/sh.md +++ b/config/sh/sh.md @@ -7430,18 +7430,18 @@ label: ;; Q/r has to come first, otherwise PC relative loads might wrongly get ;; placed into delay slots. Since there is no QImode PC relative load, the ;; Q constraint and general_movsrc_operand will reject it for QImode. -;; The Snd alternatives should come before Sdd in order to avoid a preference -;; of using r0 als the register operand for addressing modes other than -;; displacement addressing. +;; The Sid/Ssd alternatives should come before Sdd in order to avoid +;; a preference of using r0 als the register operand for addressing modes +;; other than displacement addressing. Sid/z is disparaged by '^'. ;; The Sdd alternatives allow only r0 as register operand, even though on ;; SH2A any register could be allowed by switching to a 32 bit insn. ;; Generally sticking to the r0 is preferrable, since it generates smaller ;; code. Obvious r0 reloads can then be eliminated with a peephole on SH2A. (define_insn "*mov" [(set (match_operand:QIHI 0 "general_movdst_operand" - "=r,r,r,Snd,r, Sdd,z, r,l") + "=r,r,r,Sid,^zr,Ssd,r, Sdd,z, r,l") (match_operand:QIHI 1 "general_movsrc_operand" - "Q,r,i,r, Snd,z, Sdd,l,r"))] + "Q,r,i,^zr,Sid,r, Ssd,z, Sdd,l,r"))] "TARGET_SH1 && (arith_reg_operand (operands[0], mode) || arith_reg_operand (operands[1], mode))" @@ -7453,9 +7453,11 @@ label: mov. %1,%0 mov. %1,%0 mov. %1,%0 + mov. %1,%0 + mov. %1,%0 sts %1,%0 lds %1,%0" - [(set_attr "type" "pcload,move,movi8,store,load,store,load,prget,prset") + [(set_attr "type" "pcload,move,movi8,store,load,store,load,store,load,prget,prset") (set (attr "length") (cond [(and (match_operand 0 "displacement_mem_operand") (not (match_operand 0 "short_displacement_mem_operand")))