From patchwork Mon Mar 2 23:55:20 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 445494 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id B3F9D14010F for ; Tue, 3 Mar 2015 10:56:18 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass reason="1024-bit key; unprotected key" header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=aeEroWig; dkim-adsp=none (unprotected policy); dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:mime-version:content-type; q=dns; s= default; b=LD8u3pG/OTCWWcZ2QPHKX7Cg/bLxGnhD8apON+lZuWaepDPnyX5eB Un6VvfkrQHGFovx5Ge0xSIsmWnQ0XNewjhx8Bm4Nzp+Nct2ZtJEB3lGhTcmvALW3 D+paNczDl+iPk7ePFGBemD7ei/A4FMmnQnT54XUN/vOThNpbLJhGoI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:mime-version:content-type; s= default; bh=pOMLZUst9+K81tL2QyMACisyE8M=; b=aeEroWigAXl2mI889o39 TVxZ9uSPEmKMxQ7OeZIKo2pko1m1C1YLagrRBs/hTrGPgfMDBwC+BcTBVs47SQE6 MizocRIFq1zm/3Rz4Pd36N1egY9BsjlDzeb1gdiD4lI7JrX/rdeIVixLPc5V2Bc1 cBqxNPdTuEmfClYHJ4rNyaE= Received: (qmail 59185 invoked by alias); 2 Mar 2015 23:56:10 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 59168 invoked by uid 89); 2 Mar 2015 23:56:10 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.6 required=5.0 tests=AWL, BAYES_00 autolearn=ham version=3.3.2 X-HELO: e33.co.us.ibm.com Received: from e33.co.us.ibm.com (HELO e33.co.us.ibm.com) (32.97.110.151) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Mon, 02 Mar 2015 23:56:07 +0000 Received: from /spool/local by e33.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 2 Mar 2015 16:56:03 -0700 Received: from b03cxnp07029.gho.boulder.ibm.com (b03cxnp07029.gho.boulder.ibm.com [9.17.130.16]) by d03dlp01.boulder.ibm.com (Postfix) with ESMTP id 46C9B1FF0025 for ; Mon, 2 Mar 2015 16:47:14 -0700 (MST) Received: from d03av04.boulder.ibm.com (d03av04.boulder.ibm.com [9.17.195.170]) by b03cxnp07029.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t22Nu2OL49348800 for ; Mon, 2 Mar 2015 16:56:02 -0700 Received: from d03av04.boulder.ibm.com (loopback [127.0.0.1]) by d03av04.boulder.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t22NtbIY024125 for ; Mon, 2 Mar 2015 16:55:37 -0700 Received: from ibm-tiger.the-meissners.org (dhcp-9-32-77-111.usma.ibm.com [9.32.77.111]) by d03av04.boulder.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id t22NtbZR023272; Mon, 2 Mar 2015 16:55:37 -0700 Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id A7C2E45F22; Mon, 2 Mar 2015 18:55:20 -0500 (EST) Date: Mon, 2 Mar 2015 18:55:20 -0500 From: Michael Meissner To: gcc-patches@gcc.gnu.org, dje.gcc@gmail.com Subject: [PATCH] PR 65138, Fix PowerPC little endian -flto bugs Message-ID: <20150302235520.GA17032@ibm-tiger.the-meissners.org> Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, dje.gcc@gmail.com MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15030223-0009-0000-0000-000009352F3C X-IsSubscribed: yes This patch fixes PR 65138, which shows up when you configure a compiler on a 64-bit PowerPC little endian system without using the --with-cpu=power8 configuration option, and run tests involve -flto. The following tests now run when I build a configuration without the --with-cpu=power8 option: c-c++-common/torture/vector-compare-1.c gcc.c-torture/execute/20050604-1.c gcc.c-torture/execute/20060420-1.c gcc.dg/torture/pr45678-1.c gcc.dg/torture/pr45678-2.c gcc.dg/torture/vector-1.c gcc.dg/torture/vector-2.c There were no regressions in the run. Is it ok to install in the trunk and to back port to GCC 4.9 (and GCC 4.8 if it is still active)? 2015-03-02 Michael Meissner PR 65138/target * config/rs6000/rs6000-cpus.def (powerpc64le): Add new generic processor type for 64-bit little endian PowerPC. * config/rs6000/rs6000.c (rs6000_option_override_internal): If -mdebug=reg, print TARGET_DEFAULT. Fix logic to use TARGET_DEFAULT if there is no default cpu. Fix -mdebug=reg printing built-in mask so it does not pass NULL pointers. * doc/invoke.texi (IBM RS/6000 and PowerPC options): Document -mcpu=powerpc64le. Index: gcc/config/rs6000/rs6000-cpus.def =================================================================== --- gcc/config/rs6000/rs6000-cpus.def (revision 221117) +++ gcc/config/rs6000/rs6000-cpus.def (working copy) @@ -193,4 +193,5 @@ RS6000_CPU ("power7", PROCESSOR_POWER7, RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER) RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64) +RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER) RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64) Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 221117) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -3211,6 +3211,10 @@ rs6000_option_override_internal (bool gl = ((global_init_p || target_option_default_node == NULL) ? NULL : TREE_TARGET_OPTION (target_option_default_node)); + /* Print defaults. */ + if ((TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) && global_init_p) + rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT); + /* Remember the explicit arguments. */ if (global_init_p) rs6000_isa_flags_explicit = global_options_set.x_rs6000_isa_flags; @@ -3287,7 +3291,13 @@ rs6000_option_override_internal (bool gl } else { - const char *default_cpu = (TARGET_POWERPC64 ? "powerpc64" : "powerpc"); + /* PowerPC 64-bit LE requires at least ISA 2.07. */ + const char *default_cpu = ((!TARGET_POWERPC64) + ? "powerpc" + : ((BYTES_BIG_ENDIAN) + ? "powerpc64" + : "powerpc64le")); + rs6000_cpu_index = cpu_index = rs6000_cpu_name_lookup (default_cpu); have_cpu = false; } @@ -3306,15 +3316,18 @@ rs6000_option_override_internal (bool gl & set_masks); } else - rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable - & ~rs6000_isa_flags_explicit); - - /* If no -mcpu=, inherit any default options that were cleared via - POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize - target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched - to using rs6000_isa_flags, we need to do the initialization here. */ - if (!have_cpu) - rs6000_isa_flags |= (TARGET_DEFAULT & ~rs6000_isa_flags_explicit); + { + /* If no -mcpu=, inherit any default options that were cleared via + POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize + target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched + to using rs6000_isa_flags, we need to do the initialization here. + + If there is a TARGET_DEFAULT, use that. Otherwise fall back to using + -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */ + HOST_WIDE_INT flags = ((TARGET_DEFAULT) ? TARGET_DEFAULT + : processor_target_table[cpu_index].target_enable); + rs6000_isa_flags |= (flags & ~rs6000_isa_flags_explicit); + } if (rs6000_tune_index >= 0) tune_index = rs6000_tune_index; @@ -4214,12 +4227,8 @@ rs6000_option_override_internal (bool gl target_flags. */ rs6000_builtin_mask = rs6000_builtin_mask_calculate (); if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET) - { - fprintf (stderr, - "new builtin mask = " HOST_WIDE_INT_PRINT_HEX ", ", - rs6000_builtin_mask); - rs6000_print_builtin_options (stderr, 0, NULL, rs6000_builtin_mask); - } + rs6000_print_builtin_options (stderr, 0, "builtin mask", + rs6000_builtin_mask); /* Initialize all of the registers. */ rs6000_init_hard_regno_mode_ok (global_init_p); Index: gcc/doc/invoke.texi =================================================================== --- gcc/doc/invoke.texi (revision 221117) +++ gcc/doc/invoke.texi (working copy) @@ -18628,12 +18628,13 @@ Supported values for @var{cpu_type} are @samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5}, @samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8}, @samp{powerpc}, -@samp{powerpc64}, and @samp{rs64}. +@samp{powerpc64}, @samp{powerpc64le}, and @samp{rs64}. -@option{-mcpu=powerpc}, and @option{-mcpu=powerpc64} specify pure 32-bit -PowerPC and 64-bit PowerPC architecture machine -types, with an appropriate, generic processor model assumed for -scheduling purposes. +@option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and +@option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either +endian), 64-bit big endian PowerPC and 64-bit little endian PowerPC +architecture machine types, with an appropriate, generic processor +model assumed for scheduling purposes. The other options specify a specific processor. Code generated under those options runs best on that processor, and may not run at all on