From patchwork Wed Feb 4 16:16:50 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 436419 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 490DE140218 for ; Thu, 5 Feb 2015 03:17:26 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:reply-to:mime-version:content-type; q=dns; s=default; b=or5/SS2mgYdNTu5+I7I5GdAHNdFGMzcr6fFDfsJvwdU Tg8hxpp3hO2ZVA7seixGmtHeth3wPEaLYoHsxdft9euqaQIcc+ycDXlyZqmH4yef 6nImVdMD/8jNPe8cDkmn7EHYau4nIawJY7fQYyQrOM1aDU5iuO8hTo7XnZu+Vyz4 = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:reply-to:mime-version:content-type; s=default; bh=FYI4RXZPw2+LZJKAE0lf/fCIjE4=; b=NcqzUtKIcJwYT/rGN UWdYA3awkJr0zOY4Gz+md92tqsSto6ZIqTVtvm4yWBVpCmDq/w7dmZJiYUPXQFfi WF58RuzeivgkWSd0WWeeKhQcc59PmTVzb3O4eRwmY/Nn4qF4bGNYwrnGc1rjGGOB K8vQ0FyGEVq6uhePy/DKALs2oE= Received: (qmail 32509 invoked by alias); 4 Feb 2015 16:16:54 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 32497 invoked by uid 89); 4 Feb 2015 16:16:53 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.9 required=5.0 tests=AWL, BAYES_00, NO_DNS_FOR_FROM, T_RP_MATCHES_RCVD autolearn=no version=3.3.2 X-HELO: mga11.intel.com Received: from mga11.intel.com (HELO mga11.intel.com) (192.55.52.93) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 04 Feb 2015 16:16:53 +0000 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP; 04 Feb 2015 08:16:50 -0800 X-ExtLoop1: 1 Received: from gnu-6.sc.intel.com ([172.25.70.151]) by orsmga002.jf.intel.com with ESMTP; 04 Feb 2015 08:16:51 -0800 Received: by gnu-6.sc.intel.com (Postfix, from userid 1000) id 3BC79200BBA; Wed, 4 Feb 2015 08:16:50 -0800 (PST) Date: Wed, 4 Feb 2015 08:16:50 -0800 From: "H.J. Lu" To: gcc-patches@gcc.gnu.org, Jeff Law , Vladimir Makarov Subject: [PATCH] PR rtl-optimization/64905: Clear hard frame pointer alignment if not needed Message-ID: <20150204161650.GA26675@intel.com> Reply-To: "H.J. Lu" MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.23 (2014-03-12) When hard frame pointer isn't needed, the register for hard frame pointer may be reused. This patch clears alignment on hard frame pointer if hard frame pointer isn't needed. OK for trunk after bootstrap and test on Linux/x86-64? Thanks. H.J. --- gcc/ PR rtl-optimization/64905 * ira.c (ira_setup_eliminable_regset): Clear hard frame pointer alignment if it isn't needed. gcc/testsuite/ PR rtl-optimization/64905 * gcc.target/i386/pr64905.c: New file. --- gcc/ira.c | 2 ++ gcc/testsuite/gcc.target/i386/pr64905.c | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/pr64905.c diff --git a/gcc/ira.c b/gcc/ira.c index ea2b69f..a7cf476 100644 --- a/gcc/ira.c +++ b/gcc/ira.c @@ -2313,6 +2313,8 @@ ira_setup_eliminable_regset (void) if (frame_pointer_needed) df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM, true); + else + REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = 0; COPY_HARD_REG_SET (ira_no_alloc_regs, no_unit_alloc_regs); CLEAR_HARD_REG_SET (eliminable_regset); diff --git a/gcc/testsuite/gcc.target/i386/pr64905.c b/gcc/testsuite/gcc.target/i386/pr64905.c new file mode 100644 index 0000000..bc87d85 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr64905.c @@ -0,0 +1,22 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-Os -ffixed-rax -ffixed-rbx -ffixed-rcx -ffixed-rdx -ffixed-rdi -ffixed-rsi -ffixed-r8 -ffixed-r9 -ffixed-r10 -ffixed-r11 -ffixed-r12 -ffixed-r13 -ffixed-r14 -ffixed-r15" } */ +/* { dg-final { scan-assembler-not "movl\[ \t\]0\\(%.*\\), %.*" } } */ + +typedef unsigned short uint16_t; +uint16_t a_global; + +void __attribute__ ((noinline)) +function (uint16_t **a_p) +{ + // unaligned access by address in %rbp: mov 0x0(%rbp),%ebp + a_global = **a_p; +} + +int main(int argc, char **argv) +{ + uint16_t array [4] = { 1, 2, 3, 4 }; + uint16_t *array_elem_p = &array [3]; + + function (&array_elem_p); + return 0; +}