From patchwork Fri Nov 21 11:50:20 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Tocar X-Patchwork-Id: 413024 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 2372714018C for ; Fri, 21 Nov 2014 22:50:42 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; q=dns; s=default; b=rsrfQn6q0xH418hnv uCwmInWVqJeJW7sZjR/v3H+rOqYeeaQIH1g16AwPNCl3enMQANmXpUj6P75vmX72 G/4gj+2s7Wm2xMYQEbOuWszBMrOSRZ5MJz4B2WRrw7H7RmHD0eyf73QbjG53E0c3 gQbesoBho8/cs73jL5IHuT/lWs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; s=default; bh=EkqAQWPNyVGb8Mp3MvYF/Zm qIr8=; b=WKpgkh9SWs8igbTj6S/GV80LU1/QL9/HRkAGOJXKwnZXO2ZDMl1FAuQ 2clEg1HYBQAWMVUZDSWySP+EmD/xq3FD6PNUtZ47L88h4xs6sWQgio+tIyTLtL1T bPVTabOUmk/l0ztj8RwLTK95a2K0opekDqiLx67mBov5OJrUOOb4= Received: (qmail 24335 invoked by alias); 21 Nov 2014 11:50:34 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 24320 invoked by uid 89); 21 Nov 2014 11:50:34 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=2.0 required=5.0 tests=AWL, BAYES_80, FREEMAIL_FROM, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=no version=3.3.2 X-HELO: mail-ie0-f170.google.com Received: from mail-ie0-f170.google.com (HELO mail-ie0-f170.google.com) (209.85.223.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Fri, 21 Nov 2014 11:50:31 +0000 Received: by mail-ie0-f170.google.com with SMTP id rd18so4741107iec.15 for ; Fri, 21 Nov 2014 03:50:29 -0800 (PST) X-Received: by 10.50.111.110 with SMTP id ih14mr3073893igb.38.1416570629222; Fri, 21 Nov 2014 03:50:29 -0800 (PST) Received: from msticlxl7.ims.intel.com (jfdmzpr05-ext.jf.intel.com. [134.134.139.74]) by mx.google.com with ESMTPSA id i126sm2789225ioe.28.2014.11.21.03.50.26 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 21 Nov 2014 03:50:28 -0800 (PST) Date: Fri, 21 Nov 2014 14:50:20 +0300 From: Ilya Tocar To: Uros Bizjak Cc: GCC Patches , Richard Biener , Jakub Jelinek Subject: Re: [PATCH][x86] Add clwb,pcommit,avx512avbmi,avx512ifma. Message-ID: <20141121115020.GD2323@msticlxl7.ims.intel.com> References: <20141119173254.GA116472@msticlxl7.ims.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) X-IsSubscribed: yes On 20 Nov 09:43, Uros Bizjak wrote: > On Wed, Nov 19, 2014 at 6:32 PM, Ilya Tocar wrote: > > Hi, > > > > New revision of Intel ISA reference [1] has new instructions: > > Clwb, pcommit and new flavors of AVX512. Patch bellow adds them. > > I understand that stage 1 is closed, however those changes shouldn't > > affect anything outside if i386 backend. And are extremely unlikely to > > break existing functionality, and I personally think it's desirable for > > newest GCC to support newest spec. > > Bootstrapped/regtestsed on x86_64-unknown-linux-gnu. > > Ok for trunk? > > Please split the patch into patch series, like it was done previously > for AVX512F patches. > > Uros. > > > [1]:https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf > > This part adds pcommit. Bootstrapps/passes make check. Ok for trunk? gcc/ * common/config/i386/i386-common.c (OPTION_MASK_ISA_PCOMMIT_UNSET, OPTION_MASK_ISA_PCOMMIT_SET): New. (ix86_handle_option): Handle OPT_mpcommit. * config.gcc: Add pcommitintrin.h * config/i386/pcommitintrin.h: New file. * config/i386/cpuid.h (bit_PCOMMIT): Define. * config/i386/driver-i386.c (host_detect_local_cpu): Detect pcommit. * config/i386/i386-c.c (ix86_target_macros_internal): Define __PCOMMIT__. * config/i386/i386.c (ix86_target_string): Add -mpcommit. (PTA_PCOMMIT): Define. (ix86_option_override_internal): Handle new option. (ix86_valid_target_attribute_inner_p): Add pcommit. (ix86_builtins): Add IX86_BUILTIN_PCOMMIT. (bdesc_special_args): Add __builtin_ia32_pcommit. * config/i386/i386.h (TARGET_PCOMMIT, TARGET_PCOMMIT_P): Define. * config/i386/i386.md (unspecv): Add UNSPECV_PCOMMIT. (pcommit): New instruction. * config/i386/i386.opt: Add mpcommit. * config/i386/x86intrin.h: Include pcommitintrin.h. --- gcc/common/config/i386/i386-common.c | 15 ++++++++++ gcc/config.gcc | 4 +-- gcc/config/i386/cpuid.h | 1 + gcc/config/i386/driver-i386.c | 5 +++- gcc/config/i386/i386-c.c | 2 ++ gcc/config/i386/i386.c | 12 ++++++++ gcc/config/i386/i386.h | 2 ++ gcc/config/i386/i386.md | 10 +++++++ gcc/config/i386/i386.opt | 4 +++ gcc/config/i386/pcommitintrin.h | 49 +++++++++++++++++++++++++++++++ gcc/config/i386/x86intrin.h | 2 ++ gcc/testsuite/g++.dg/other/i386-2.C | 2 +- gcc/testsuite/g++.dg/other/i386-3.C | 2 +- gcc/testsuite/gcc.target/i386/pcommit-1.c | 11 +++++++ gcc/testsuite/gcc.target/i386/sse-12.c | 2 +- gcc/testsuite/gcc.target/i386/sse-13.c | 2 +- gcc/testsuite/gcc.target/i386/sse-14.c | 2 +- gcc/testsuite/gcc.target/i386/sse-22.c | 2 +- gcc/testsuite/gcc.target/i386/sse-23.c | 2 +- 19 files changed, 121 insertions(+), 10 deletions(-) create mode 100644 gcc/config/i386/pcommitintrin.h create mode 100644 gcc/testsuite/gcc.target/i386/pcommit-1.c diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index bad0988..2e09d77 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -86,6 +86,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_XSAVEC_SET \ (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE) #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB +#define OPTION_MASK_ISA_PCOMMIT_SET OPTION_MASK_ISA_PCOMMIT /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same as -msse4.2. */ @@ -182,6 +183,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES +#define OPTION_MASK_ISA_PCOMMIT_UNSET OPTION_MASK_ISA_PCOMMIT #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same @@ -903,6 +905,19 @@ ix86_handle_option (struct gcc_options *opts, } return true; + case OPT_mpcommit: + if (value) + { + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCOMMIT_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCOMMIT_SET; + } + else + { + opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCOMMIT_UNSET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCOMMIT_UNSET; + } + return true; + case OPT_mclwb: if (value) { diff --git a/gcc/config.gcc b/gcc/config.gcc index 766f13b..fa3e1fc 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -369,7 +369,7 @@ i[34567]86-*-*) xsavesintrin.h avx512dqintrin.h avx512bwintrin.h avx512vlintrin.h avx512vlbwintrin.h avx512vldqintrin.h avx512ifmaintrin.h avx512ifmavlintrin.h avx512vbmiintrin.h - avx512vbmivlintrin.h clwbintrin.h" + avx512vbmivlintrin.h clwbintrin.h pcommitintrin.h" ;; x86_64-*-*) cpu_type=i386 @@ -390,7 +390,7 @@ x86_64-*-*) xsavesintrin.h avx512dqintrin.h avx512bwintrin.h avx512vlintrin.h avx512vlbwintrin.h avx512vldqintrin.h avx512ifmaintrin.h avx512ifmavlintrin.h avx512vbmiintrin.h - avx512vbmivlintrin.h clwbintrin.h" + avx512vbmivlintrin.h clwbintrin.h pcommitintrin.h" ;; ia64-*-*) extra_headers=ia64intrin.h diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index 6ee928b..6c6e7f3 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -77,6 +77,7 @@ #define bit_RDSEED (1 << 18) #define bit_ADX (1 << 19) #define bit_AVX512IFMA (1 << 21) +#define bit_PCOMMIT (1 << 22) #define bit_CLFLUSHOPT (1 << 23) #define bit_CLWB (1 << 24) #define bit_AVX512PF (1 << 26) diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index c7acfba..a2248ce 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -413,6 +413,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) unsigned int has_clflushopt = 0, has_xsavec = 0, has_xsaves = 0; unsigned int has_avx512dq = 0, has_avx512bw = 0, has_avx512vl = 0; unsigned int has_avx512vbmi = 0, has_avx512ifma = 0, has_clwb = 0; + unsigned int has_pcommit = 0; bool arch; @@ -490,6 +491,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) has_avx512pf = ebx & bit_AVX512PF; has_avx512cd = ebx & bit_AVX512CD; has_sha = ebx & bit_SHA; + has_pcommit = ebx & bit_PCOMMIT; has_clflushopt = ebx & bit_CLFLUSHOPT; has_clwb = ebx & bit_CLWB; has_avx512dq = ebx & bit_AVX512DQ; @@ -932,6 +934,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) const char *avx512ifma = has_avx512ifma ? " -mavx512ifma" : " -mno-avx512ifma"; const char *avx512vbmi = has_avx512vbmi ? " -mavx512vbmi" : " -mno-avx512vbmi"; const char *clwb = has_clwb ? " -mclwb" : " -mno-clwb"; + const char *pcommit = has_pcommit ? " -mpcommit" : " -mno-pcommit"; options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3, sse4a, cx16, sahf, movbe, aes, sha, pclmul, @@ -941,7 +944,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) fxsr, xsave, xsaveopt, avx512f, avx512er, avx512cd, avx512pf, prefetchwt1, clflushopt, xsavec, xsaves, avx512dq, avx512bw, avx512vl, - avx512ifma, avx512vbmi, clwb, NULL); + avx512ifma, avx512vbmi, clwb, pcommit, NULL); } done: diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index 9742536..3ad7d49 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -411,6 +411,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__XSAVES__"); if (isa_flag & OPTION_MASK_ISA_MPX) def_or_undef (parse_in, "__MPX__"); + if (isa_flag & OPTION_MASK_ISA_PCOMMIT) + def_or_undef (parse_in, "__PCOMMIT__"); if (isa_flag & OPTION_MASK_ISA_CLWB) def_or_undef (parse_in, "__CLWB__"); } diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index e470b48..3d186e3 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -2658,6 +2658,7 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch, { "-mxsaves", OPTION_MASK_ISA_XSAVES }, { "-mmpx", OPTION_MASK_ISA_MPX }, { "-mclwb", OPTION_MASK_ISA_CLWB }, + { "-mpcommit", OPTION_MASK_ISA_PCOMMIT }, }; /* Flag options. */ @@ -3159,6 +3160,7 @@ ix86_option_override_internal (bool main_args_p, #define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 53) #define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 54) #define PTA_CLWB (HOST_WIDE_INT_1 << 55) +#define PTA_PCOMMIT (HOST_WIDE_INT_1 << 56) #define PTA_CORE2 \ (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \ @@ -3718,6 +3720,9 @@ ix86_option_override_internal (bool main_args_p, if (processor_alias_table[i].flags & PTA_PREFETCHWT1 && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PREFETCHWT1)) opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1; + if (processor_alias_table[i].flags & PTA_PCOMMIT + && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PCOMMIT)) + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCOMMIT; if (processor_alias_table[i].flags & PTA_CLWB && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CLWB)) opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB; @@ -4667,6 +4672,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[], IX86_ATTR_ISA ("avx512vbmi", OPT_mavx512vbmi), IX86_ATTR_ISA ("avx512ifma", OPT_mavx512ifma), IX86_ATTR_ISA ("clwb", OPT_mclwb), + IX86_ATTR_ISA ("pcommit", OPT_mpcommit), /* enum options */ IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_), @@ -30105,6 +30111,9 @@ enum ix86_builtins /* CLWB instructions. */ IX86_BUILTIN_CLWB, + /* PCOMMIT instructions. */ + IX86_BUILTIN_PCOMMIT, + /* CLFLUSHOPT instructions. */ IX86_BUILTIN_CLFLUSHOPT, @@ -30865,6 +30874,9 @@ static const struct builtin_description bdesc_special_args[] = { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI }, { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI }, { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI }, + + /* PCOMMIT. */ + { OPTION_MASK_ISA_PCOMMIT, CODE_FOR_pcommit, "__builtin_ia32_pcommit", IX86_BUILTIN_PCOMMIT, UNKNOWN, (int) VOID_FTYPE_VOID }, }; /* Builtins with variable number of arguments. */ diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 03d1b06..3f5f979 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -150,6 +150,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_PREFETCHWT1_P(x) TARGET_ISA_PREFETCHWT1_P(x) #define TARGET_MPX TARGET_ISA_MPX #define TARGET_MPX_P(x) TARGET_ISA_MPX_P(x) +#define TARGET_PCOMMIT TARGET_ISA_PCOMMIT +#define TARGET_PCOMMIT_P(x) TARGET_ISA_PCOMMIT_P(x) #define TARGET_CLWB TARGET_ISA_CLWB #define TARGET_CLWB_P(x) TARGET_ISA_CLWB_P(x) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index a60e2de..b3b8af6 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -256,6 +256,9 @@ ;; For CLWB support UNSPECV_CLWB + ;; For PCOMMIT support + UNSPECV_PCOMMIT + ;; For CLFLUSHOPT support UNSPECV_CLFLUSHOPT ]) @@ -18671,6 +18674,13 @@ [(set_attr "type" "other") (set_attr "length" "3")]) +(define_insn "pcommit" + [(unspec_volatile [(const_int 0)] UNSPECV_PCOMMIT)] + "TARGET_PCOMMIT" + "pcommit" + [(set_attr "type" "other") + (set_attr "length" "4")]) + (define_insn "clwb" [(unspec_volatile [(match_operand 0 "address_operand" "p")] UNSPECV_CLWB)] diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 9c18173..c6d6e25 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -725,6 +725,10 @@ mclwb Target Report Mask(ISA_CLWB) Var(ix86_isa_flags) Save Support CLWB instructions +mpcommit +Target Report Mask(ISA_PCOMMIT) Var(ix86_isa_flags) Save +Support PCOMMIT instructions + mfxsr Target Report Mask(ISA_FXSR) Var(ix86_isa_flags) Save Support FXSAVE and FXRSTOR instructions diff --git a/gcc/config/i386/pcommitintrin.h b/gcc/config/i386/pcommitintrin.h new file mode 100644 index 0000000..b3a802e --- /dev/null +++ b/gcc/config/i386/pcommitintrin.h @@ -0,0 +1,49 @@ +/* Copyright (C) 2013 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#if !defined _X86INTRIN_H_INCLUDED +# error "Never use directly; include instead." +#endif + +#ifndef _PCOMMITINTRIN_H_INCLUDED +#define _PCOMMITINTRIN_H_INCLUDED + +#ifndef __PCOMMIT__ +#pragma GCC push_options +#pragma GCC target("pcommit") +#define __DISABLE_PCOMMIT__ +#endif /* __PCOMMIT__ */ + +extern __inline void +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_pcommit (void) +{ + __builtin_ia32_pcommit (); +} + +#ifdef __DISABLE_PCOMMIT__ +#undef __DISABLE_PCOMMIT__ +#pragma GCC pop_options +#endif /* __DISABLE_PCOMMIT__ */ + +#endif /* _PCOMMITINTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/x86intrin.h b/gcc/config/i386/x86intrin.h index 7f9a519..fdb613f 100644 --- a/gcc/config/i386/x86intrin.h +++ b/gcc/config/i386/x86intrin.h @@ -77,6 +77,8 @@ #include +#include + #include #include diff --git a/gcc/testsuite/g++.dg/other/i386-2.C b/gcc/testsuite/g++.dg/other/i386-2.C index dbbe0bc..4f77dd7 100644 --- a/gcc/testsuite/g++.dg/other/i386-2.C +++ b/gcc/testsuite/g++.dg/other/i386-2.C @@ -1,5 +1,5 @@ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mclwb" } */ +/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mclwb -mpcommit" } */ /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, diff --git a/gcc/testsuite/g++.dg/other/i386-3.C b/gcc/testsuite/g++.dg/other/i386-3.C index 185f403..53b90b8 100644 --- a/gcc/testsuite/g++.dg/other/i386-3.C +++ b/gcc/testsuite/g++.dg/other/i386-3.C @@ -1,5 +1,5 @@ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mclwb" } */ +/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mclwb -mpcommit" } */ /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, diff --git a/gcc/testsuite/gcc.target/i386/pcommit-1.c b/gcc/testsuite/gcc.target/i386/pcommit-1.c new file mode 100644 index 0000000..dc4bc9d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pcommit-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mpcommit" } */ +/* { dg-final { scan-assembler "pcommit" } } */ + +#include "x86intrin.h" + +void +test_pcommit () +{ + _mm_pcommit (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c index 9af6f70..bdb0e10 100644 --- a/gcc/testsuite/gcc.target/i386/sse-12.c +++ b/gcc/testsuite/gcc.target/i386/sse-12.c @@ -3,7 +3,7 @@ popcntintrin.h and mm_malloc.h are usable with -O -std=c89 -pedantic-errors. */ /* { dg-do compile } */ -/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512ifma -mclwb" } */ +/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512ifma -mclwb -mpcommit" } */ #include diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c index 98b0936..104c63e 100644 --- a/gcc/testsuite/gcc.target/i386/sse-13.c +++ b/gcc/testsuite/gcc.target/i386/sse-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512ifma -mclwb" } */ +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512ifma -mclwb -mpcommit" } */ #include diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c index 3c462c0..f3f6c5c 100644 --- a/gcc/testsuite/gcc.target/i386/sse-14.c +++ b/gcc/testsuite/gcc.target/i386/sse-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mclwb" } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mclwb -mpcommit" } */ /* { dg-add-options bind_pic_locally } */ #include diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c index b1def10..0d7bd16 100644 --- a/gcc/testsuite/gcc.target/i386/sse-22.c +++ b/gcc/testsuite/gcc.target/i386/sse-22.c @@ -695,7 +695,7 @@ test_2 (_mm_clmulepi64_si128, __m128i, __m128i, __m128i, 1) /* x86intrin.h (FMA4/XOP/LWP/BMI/BMI2/TBM/LZCNT/FMA). */ #ifdef DIFFERENT_PRAGMAS -#pragma GCC target ("fma4,xop,lwp,bmi,bmi2,tbm,lzcnt,fma,rdseed,prfchw,adx,fxsr,xsaveopt,xsavec,xsaves,clflushopt,clwb") +#pragma GCC target ("fma4,xop,lwp,bmi,bmi2,tbm,lzcnt,fma,rdseed,prfchw,adx,fxsr,xsaveopt,xsavec,xsaves,clflushopt,clwb,pcommit") #endif #include /* xopintrin.h */ diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c index 5f149cb..9f81a8a 100644 --- a/gcc/testsuite/gcc.target/i386/sse-23.c +++ b/gcc/testsuite/gcc.target/i386/sse-23.c @@ -594,7 +594,7 @@ #define __builtin_ia32_extracti64x2_256_mask(A, E, C, D) __builtin_ia32_extracti64x2_256_mask(A, 1, C, D) #define __builtin_ia32_extractf64x2_256_mask(A, E, C, D) __builtin_ia32_extractf64x2_256_mask(A, 1, C, D) -#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,clwb") +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,clwb,pcommit") #include #include #include