From patchwork Wed Nov 20 12:32:59 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Enkovich X-Patchwork-Id: 292752 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 13FBD2C00C3 for ; Wed, 20 Nov 2013 23:34:11 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; q=dns; s=default; b=DfHxH7+RGbhGq9IkB nd8MQ9lGIORskZFAHy12m+FRjNkhQN7reTVqnF49tbd2nyUAsMAIpZzKZVZUS5YI ySm20RWG9FibFImL1oEqi3/ldbU8g9uYZhY9phEP9EzMoxrldrY4pu/DxWNlGPW+ kr8C2LAkHctWpiGbCEwZdZyCdM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; s=default; bh=QN54gg1nwHTfMxWyesfpx5s 4PlU=; b=IR7HT/tg3Lw2xBMvokS46fAUUAGfVbEcfy803EEjWxcDQ8Cxxxu3t6A N13QyK84sb3SC8ri772rMaV28Es0azjCU1ppJU499M4UtIBvPeNVpmIfrWFOHQy6 63xpXoosgOF3YjInON9Dkbo6xWHgdG+vfv/g+VDksOEdgvaJzStk= Received: (qmail 17280 invoked by alias); 20 Nov 2013 12:34:00 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 17268 invoked by uid 89); 20 Nov 2013 12:34:00 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=2.6 required=5.0 tests=AWL, BAYES_99, FREEMAIL_FROM, RDNS_NONE, SPF_PASS, URIBL_BLOCKED autolearn=no version=3.3.2 X-HELO: mail-pa0-f41.google.com Received: from Unknown (HELO mail-pa0-f41.google.com) (209.85.220.41) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Wed, 20 Nov 2013 12:33:59 +0000 Received: by mail-pa0-f41.google.com with SMTP id lf10so2655809pab.0 for ; Wed, 20 Nov 2013 04:33:51 -0800 (PST) X-Received: by 10.68.49.232 with SMTP id x8mr377039pbn.167.1384950831249; Wed, 20 Nov 2013 04:33:51 -0800 (PST) Received: from msticlxl57.ims.intel.com (fmdmzpr03-ext.fm.intel.com. [192.55.54.38]) by mx.google.com with ESMTPSA id rx4sm42619188pab.13.2013.11.20.04.33.49 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 20 Nov 2013 04:33:50 -0800 (PST) Date: Wed, 20 Nov 2013 16:32:59 +0400 From: Ilya Enkovich To: Uros Bizjak Cc: "gcc-patches@gcc.gnu.org" Subject: Re: [PATCH, i386, MPX, 2/X] Pointers Checker [21/25] Size relocation Message-ID: <20131120123259.GA53216@msticlxl57.ims.intel.com> References: <20131119204344.GU21297@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes On 20 Nov 09:49, Uros Bizjak wrote: > On Tue, Nov 19, 2013 at 9:43 PM, Ilya Enkovich wrote: > > >> > Here is a patch to add size relocation and instruction to obtain object's size in i386 target. > >> > >> +(define_insn "move_size_reloc_" > >> + [(set (match_operand:SWI48 0 "register_operand" "=r") > >> + (match_operand: 1 "size_relocation" "Z"))] > >> + "" > >> +{ > >> + return "mov{}\t{%1, %0|%0, %1}"; > >> > >> Please don't change x86_64_immediate_operand just to use "Z" > >> constraint The predicate is used in a couple of other places that for > >> sure don't accept your change. > >> > >> Better write this insn in an explicit way (see for example > >> tls_initial_exec_64_sun). Something like: > >> > >> (define_insn "move_size_reloc_" > >> [(set (match_operand:SWI48 0 "register_operand" "=r") > >> (unspec:SWI48 > >> [(match_operand 1 "symbolic_operand" "..." )] > >> UNSPEC_SIZEOF))] > >> "" > >> "mov{}\t{%a1@SIZE, %0|%0, %a1@SIZE}") > >> > >> You will probably need to define new operand 1 predicate and constraint. > >> > >> Uros. > > > > Hi, Uros! Thanks for comments! Here is what I got trying to follow your suggestion. Does it look better? > > You actually don't need any operand modifiers in the insn template. Simply use: > > "mov{}\t{%1@SIZE, %0|%0, %1@SIZE}" > > and you will automatically get > > "movl $zzz, %eax" or "mov %eax, OFFSET FLAT: zzz". > > Since your pattern allows only symbolic_operand, there is no reload, > so you can avoid the constraint alltogether. > > BTW: Did you consider various -mcmodel=... options? For DImode moves, > you should check x86_64_zext_immediate_operand predicate and output > either "movl $zzz, %eax" or "movabs $zzz, %rax". There is no movq with > 64bit immediate. Please see movdi pattern. > > Uros. Yep, for large objects it may work wrongly. Does anyone use static objects >4Gb? :) Large address does not mean large object but seems we have to be conservative here. I added x86_64_zext_immediate_operand check with additional CM_KERNEL check because in this model object size should always fit 32 bits. Thanks, Ilya --- gcc/ 2013-11-19 Ilya Enkovich * config/i386/i386.md (UNSPEC_SIZEOF): New. (move_size_reloc_): New. * config/i386/predicates.md (symbol_operand): New. diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md index 7289ae4..b29fadb 100644 --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -241,6 +241,7 @@ ;; s - address with no segment register ;; i - address with no index and no rip ;; b - address with no base and no rip +;; S - symbol reference (define_address_constraint "Tv" "VSIB address operand" diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index e23b3b6..772c09d 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -79,6 +79,7 @@ UNSPEC_PLTOFF UNSPEC_MACHOPIC_OFFSET UNSPEC_PCREL + UNSPEC_SIZEOF ;; Prologue support UNSPEC_STACK_ALLOC @@ -18446,6 +18447,22 @@ "bndstx\t{%2, %3|%3, %2}" [(set_attr "type" "mpxst")]) +(define_insn "move_size_reloc_" + [(set (match_operand:SWI48 0 "register_operand" "=r") + (unspec: + [(match_operand: 1 "symbol_operand")] + UNSPEC_SIZEOF))] + "" +{ + if (GET_MODE (operands[0]) == SImode) + return "mov{l}\t{%1@SIZE, %k0|%k0, %1@SIZE}"; + else if (x86_64_zext_immediate_operand (operands[1], VOIDmode) + || ix86_cmodel == CM_KERNEL) + return "mov{q}\t{%1@SIZE, %0|%0, %1@SIZE}"; + else + return "movabs{q}\t{%1@SIZE, %0|%0, %1@SIZE}"; +}) + (include "mmx.md") (include "sse.md") (include "sync.md") diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 66ac52f..5c758ab 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -119,6 +119,10 @@ (match_test "TARGET_64BIT") (match_test "REGNO (op) > BX_REG"))) +;; Return true if VALUE is symbol reference +(define_predicate "symbol_operand" + (match_code "symbol_ref")) + ;; Return true if VALUE can be stored in a sign extended immediate field. (define_predicate "x86_64_immediate_operand" (match_code "const_int,symbol_ref,label_ref,const")