More improvements to sparc VIS vec_init code generation.

Eric, the testsuite target tests for vis2 and vi3 capable hardware
work well in my own testing but if you find some problem with how
it's done just let me know and I'll try to fix it up.

I'm almost %100 satisfied with the code generation for vec_init now.
The one remaining case where I think we can do better is initializing
a V8QImode vector using bshuffle with more than 4 unique inputs.

I've been trying to come up with a trick to use fpmerge to get the
last few bytes into place for the bshuffle, but it's a bit of a
challenge because the bytes don't propagate into the destination in a
convenient way.  In particular it can't be done without fighting the
natural move coalescing from the RTL optimizers that cleans up these
RTL expansions.

The vector_init_bshuffle() code tries to rely upon moves as much as
possible to put the bshuffle inputs into place, because such moves
are typically completely optimized away by the compiler.

So something like:

__v4hi foo(short a, short b, short c, short d)
{
  __v4hi x = { a, b, c, d };
  return x;
}

generates:

foo:
	movwtos	%o0, %f2
	movwtos	%o1, %f3
	movwtos	%o2, %f4
	movwtos	%o3, %f5
	sethi	%hi(bmask_val), %g1
	or	%g1, %lo(bmask_val), %g1
	bmask	%g1, %g0, %g1
	retl
	 bshuffle %f2, %f4, %f0

for VIS3.

For cases where we only load part of a register input to the bshuffle
instruction, and the rest of the register is "don't care" we have a
preceeding clobber emitted so that the compiler doesn't try to zero
initialize the uninitialized bits.

Support for the short floating point loads starts to show up here as
well, and I intend to flesh these out, support the short float stores,
and add VIS intrinsic access to them.

Richard, is there a better way to represent this in RTL?  These
instructions basically load a single byte or half-word into the bottom
of a 64-bit float register, and clear the rest of that register with
zeros.  So the v4hi one is essentially loading the vector:

	[(const_int 0) (const_int 0)
         (const_int 0) (mem:HI (register:P ...))]

into the destination 64-bit float reg.

For now I'm simply using an unspec.

Committed to trunk.

gcc/

	* config/sparc/sparc.md (UNSPEC_SHORT_LOAD): New unspec.
	(zero-extend_v8qi_vis, zero_extend_v4hi_vis): New expanders.
	(*zero_extend_v8qi_<P:mode>_insn,
	*zero_extend_v4hi_<P:mode>_insn): New insns.
	* config/sparc/sparc.c (vector_init_move_words)
	(vector_init_prepare_elts, sparc_expand_vector_init_vis2,
	sparc_expand_vector_init_vis1): New functions.
	(vector_init_bshuffle): Rewrite to handle more cases and make use
	of locs[] array prepared by vector_init_prepare_elts.
	(vector_init_fpmerge, vector_init_faligndata): Delete.
	(sparc_expand_vector_init): Rewrite using new infrastructure.

gcc/testsuite/

	* lib/test-supports.exp
	(check_effective_target_ultrasparc_vis2_hw): New proc.
	(check_effective_target_ultrasparc_vis3_hw): New proc.
	* gcc.target/sparc/vec-init-1.inc: New vector init common code.
	* gcc.target/sparc/vec-init-2.inc: Likewise.
	* gcc.target/sparc/vec-init-3.inc: Likewise.
	* gcc.target/sparc/vec-init-1-vis1.c: New test.
	* gcc.target/sparc/vec-init-1-vis2.c: New test.
	* gcc.target/sparc/vec-init-1-vis3.c: New test.
	* gcc.target/sparc/vec-init-2-vis1.c: New test.
	* gcc.target/sparc/vec-init-2-vis2.c: New test.
	* gcc.target/sparc/vec-init-2-vis3.c: New test.
	* gcc.target/sparc/vec-init-3-vis1.c: New test.
	* gcc.target/sparc/vec-init-3-vis2.c: New test.
	* gcc.target/sparc/vec-init-3-vis3.c: New test.
---
 gcc/ChangeLog                                    |   16 +-
 gcc/config/sparc/sparc.c                         |  419 +++++++++++++++++-----
 gcc/config/sparc/sparc.md                        |   43 +++
 gcc/testsuite/ChangeLog                          |   18 +
 gcc/testsuite/gcc.target/sparc/vec-init-1-vis1.c |    5 +
 gcc/testsuite/gcc.target/sparc/vec-init-1-vis2.c |    5 +
 gcc/testsuite/gcc.target/sparc/vec-init-1-vis3.c |    5 +
 gcc/testsuite/gcc.target/sparc/vec-init-1.inc    |   85 +++++
 gcc/testsuite/gcc.target/sparc/vec-init-2-vis1.c |    5 +
 gcc/testsuite/gcc.target/sparc/vec-init-2-vis2.c |    5 +
 gcc/testsuite/gcc.target/sparc/vec-init-2-vis3.c |    5 +
 gcc/testsuite/gcc.target/sparc/vec-init-2.inc    |   94 +++++
 gcc/testsuite/gcc.target/sparc/vec-init-3-vis1.c |    5 +
 gcc/testsuite/gcc.target/sparc/vec-init-3-vis2.c |    5 +
 gcc/testsuite/gcc.target/sparc/vec-init-3-vis3.c |    5 +
 gcc/testsuite/gcc.target/sparc/vec-init-3.inc    |  105 ++++++
 gcc/testsuite/lib/target-supports.exp            |   18 +
 17 files changed, 743 insertions(+), 100 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/sparc/vec-init-1-vis1.c
 create mode 100644 gcc/testsuite/gcc.target/sparc/vec-init-1-vis2.c
 create mode 100644 gcc/testsuite/gcc.target/sparc/vec-init-1-vis3.c
 create mode 100644 gcc/testsuite/gcc.target/sparc/vec-init-1.inc
 create mode 100644 gcc/testsuite/gcc.target/sparc/vec-init-2-vis1.c
 create mode 100644 gcc/testsuite/gcc.target/sparc/vec-init-2-vis2.c
 create mode 100644 gcc/testsuite/gcc.target/sparc/vec-init-2-vis3.c
 create mode 100644 gcc/testsuite/gcc.target/sparc/vec-init-2.inc
 create mode 100644 gcc/testsuite/gcc.target/sparc/vec-init-3-vis1.c
 create mode 100644 gcc/testsuite/gcc.target/sparc/vec-init-3-vis2.c
 create mode 100644 gcc/testsuite/gcc.target/sparc/vec-init-3-vis3.c
 create mode 100644 gcc/testsuite/gcc.target/sparc/vec-init-3.inc

More improvements to sparc VIS vec_init code generation.

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