PATCH: PR bootstrap/49964: Bootstrap failed with AVX turned on

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index dda8660..079d37b 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -21622,8 +21622,18 @@  ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
 	  unspec = gen_rtx_UNSPEC (VOIDmode,
 				   gen_rtvec (1, GEN_INT (avx256)),
 				   UNSPEC_CALL_NEEDS_VZEROUPPER);
-	  call = gen_rtx_PARALLEL (VOIDmode,
-				   gen_rtvec (2, call, unspec));
+	  if (GET_CODE (call) == PARALLEL)
+	    {
+	      gcc_assert (XVECLEN (call, 0) == 2);
+	      call = gen_rtx_PARALLEL (VOIDmode,
+				       gen_rtvec (3,
+						  XVECEXP (call, 0, 0),
+						  XVECEXP (call, 0, 1),
+						  unspec));
+	    }
+	  else
+	    call = gen_rtx_PARALLEL (VOIDmode,
+				     gen_rtvec (2, call, unspec));
 	}
     }
 
@@ -21637,7 +21647,21 @@  ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
 void
 ix86_split_call_vzeroupper (rtx insn, rtx vzeroupper)
 {
-  rtx call = XVECEXP (PATTERN (insn), 0, 0);
+  rtx call = PATTERN (insn);
+  switch (XVECLEN (call, 0))
+    {
+     case 2:
+       call = XVECEXP (call, 0, 0);
+       break;
+     case 3:
+       call = gen_rtx_PARALLEL (VOIDmode,
+				gen_rtvec (2,
+					   XVECEXP (call, 0, 0),
+					   XVECEXP (call, 0, 1)));
+       break;
+     default:
+       gcc_unreachable ();
+    }
   emit_insn (gen_avx_vzeroupper (vzeroupper));
   emit_call_insn (call);
 }
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 3a07d4e..3f1a9c7 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -11128,12 +11128,11 @@ 
 })
 
 (define_insn_and_split "*call_pop_vzeroupper"
-  [(parallel
-    [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lzm"))
+  [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lzm"))
 	   (match_operand:SI 1 "" ""))
-     (set (reg:SI SP_REG)
-	  (plus:SI (reg:SI SP_REG)
-		   (match_operand:SI 2 "immediate_operand" "i")))])
+   (set (reg:SI SP_REG)
+	(plus:SI (reg:SI SP_REG)
+		 (match_operand:SI 2 "immediate_operand" "i")))
    (unspec [(match_operand 3 "const_int_operand" "")]
    	   UNSPEC_CALL_NEEDS_VZEROUPPER)]
   "TARGET_VZEROUPPER && !TARGET_64BIT && !SIBLING_CALL_P (insn)"
@@ -11154,12 +11153,11 @@ 
   [(set_attr "type" "call")])
 
 (define_insn_and_split "*sibcall_pop_vzeroupper"
- [(parallel
-   [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "Uz"))
-	  (match_operand 1 "" ""))
-     (set (reg:SI SP_REG)
-	  (plus:SI (reg:SI SP_REG)
-		   (match_operand:SI 2 "immediate_operand" "i")))])
+  [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "Uz"))
+	 (match_operand 1 "" ""))
+   (set (reg:SI SP_REG)
+	(plus:SI (reg:SI SP_REG)
+		 (match_operand:SI 2 "immediate_operand" "i")))
    (unspec [(match_operand 3 "const_int_operand" "")]
    	   UNSPEC_CALL_NEEDS_VZEROUPPER)]
   "TARGET_VZEROUPPER && !TARGET_64BIT && SIBLING_CALL_P (insn)"
@@ -11310,13 +11308,12 @@ 
 })
 
 (define_insn_and_split "*call_value_pop_vzeroupper"
-  [(parallel
-    [(set (match_operand 0 "" "")
-	  (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lzm"))
-		(match_operand 2 "" "")))
-     (set (reg:SI SP_REG)
-	  (plus:SI (reg:SI SP_REG)
-		   (match_operand:SI 3 "immediate_operand" "i")))])
+  [(set (match_operand 0 "" "")
+	(call (mem:QI (match_operand:SI 1 "call_insn_operand" "lzm"))
+	      (match_operand 2 "" "")))
+   (set (reg:SI SP_REG)
+	(plus:SI (reg:SI SP_REG)
+		 (match_operand:SI 3 "immediate_operand" "i")))
    (unspec [(match_operand 4 "const_int_operand" "")]
    	   UNSPEC_CALL_NEEDS_VZEROUPPER)]
   "TARGET_VZEROUPPER && !TARGET_64BIT && !SIBLING_CALL_P (insn)"
@@ -11338,13 +11335,12 @@ 
   [(set_attr "type" "callv")])
 
 (define_insn_and_split "*sibcall_value_pop_vzeroupper"
- [(parallel
-   [(set (match_operand 0 "" "")
-	  (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "Uz"))
-		(match_operand 2 "" "")))
-     (set (reg:SI SP_REG)
-	  (plus:SI (reg:SI SP_REG)
-		   (match_operand:SI 3 "immediate_operand" "i")))])
+  [(set (match_operand 0 "" "")
+	(call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "Uz"))
+	      (match_operand 2 "" "")))
+   (set (reg:SI SP_REG)
+	(plus:SI (reg:SI SP_REG)
+		 (match_operand:SI 3 "immediate_operand" "i")))
    (unspec [(match_operand 4 "const_int_operand" "")]
    	   UNSPEC_CALL_NEEDS_VZEROUPPER)]
   "TARGET_VZEROUPPER && !TARGET_64BIT && SIBLING_CALL_P (insn)"